NEC 78011BGC AB8 Series, User Manual

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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (
µ
PD78014Y Subseries)
391
(5) Pin configurations
The configurations of the serial clock pin SCL and the serial data bus pins SDA0 (SDA1) are shown below.
(a) SCL ......................... Pin for serial clock input/output.
<1> Master ............. N-ch open-drain output
<2> Slave ............... Schmitt input
(b) SDA0 (SDA1) ......... Serial data input/output dual-function pin.
Uses N-ch open-drain output and Schmitt-input buffers for both master and slave
devices.
Both serial clock and serial data bus require the external pull-up resistors to be output by N-ch open drain.
Figure 16-44. Pin Configuration
Caution Because the N-ch open-drain output must be set to high-impedance at the time of data
reception, write FFH to the serial I/O shift register 0 (SIO0) in advance. However, when wake-
up function is used (that is, bit 5 (WUP) of serial operating mode register 0 (CSIM0) is set), do
not write FFH to SIO0 before data reception. Without writing FFH to SIO0, the N-ch open-drain
output is always high-impedance state.
V
DD
V
DD
SCL
SDA0 (SDA1)
Master device
Clock output
(Clock input)
Data output
Data input
Slave device
(Clock output)
Clock input
Data output
Data input
SCL
SDA0 (SDA1)