NEC 78011BGC AB8 Series, User Manual

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CHAPTER 23 INSTRUCTION SET
510
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
3. Except r = A
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
CPU
) selected by processor clock control
register (PCC).
2. Clock indicates when a program is in the internal ROM area.
3. n is the number of waits when the external memory expansion area is read.
Instruc- Mnemonic Operands Byte Clock Operation Flag
tion
Note 1 Note 2 Z AC CY
Group
8-bit XOR A, #byte 2 8 — A
←
A
∨
byte
×
Ope- saddr, #byte 3 12 16 (saddr)
←
(saddr)
∨
byte
×
ration A, r
Note 3
2 8 — A
←
A
∨
r
×
r, A 2 8 — r
←
r
∨
A
×
A, saddr 2 8 10 A
←
A
∨
(saddr)
×
A, !addr16 3 16 18 + 2n A
←
A
∨
(addr16)
×
A, [HL] 1 8 10 + 2n A
←
A
∨
(HL)
×
A, [HL+byte] 2 16 18 + 2n A
←
A
∨
(HL+byte)
×
A, [HL+B] 2 16 18 + 2n A
←
A
∨
(HL+B)
×
A, [HL+C] 2 16 18 + 2n A
←
A
∨
(HL+C)
×
CMP A, #byte 2 8 — A–byte
× × ×
saddr, #byte 3 12 16 (saddr)–byte
× × ×
A, r
Note 3
2 8 — A–r
× × ×
r, A 2 8 — r–A
× × ×
A, saddr 2 8 10 A–(saddr)
× × ×
A, !addr16 3 16 18 + 2n A–(addr16)
× × ×
A, [HL] 1 8 10 + 2n A–(HL)
× × ×
A, [HL+byte] 2 16 18 + 2n A–(HL+byte)
× × ×
A, [HL+B] 2 16 18 + 2n A–(HL+B)
× × ×
A, [HL+C] 2 16 18 + 2n A–(HL+C)
× × ×
16-bit ADDW AX, #word 3 12 — AX, CY
←
AX+word
× × ×
Ope- SUBW AX, #word 3 12 — AX, CY
←
AX–word
× × ×
ration CMPW AX, #word 3 12 — AX–word
× × ×
Multiply/ MULU X 2 32 — AX
←
A
×
X
Divide DIVUW C 2 50 — AX (Quotient), C (Remainder)
←
AX
÷
C