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LIST OF TABLES (3/3)

Table No.

Title, Page

20-1

HALT Mode Operating Status ........................................................................................................... 485

20-2

Operation after HALT Mode Clear .................................................................................................... 487

20-3

STOP Mode Operating Status .......................................................................................................... 488

20-4

Operation after STOP Mode Clear .................................................................................................... 490

21-1

Hardware Status after Reset ............................................................................................................. 493

22-1

Differences between

PD78P014, 78P014Y, and Mask ROM Version ............................................ 495

22-2

Internal Memory Size Switching Register Value at Reset ................................................................. 496

22-3

PROM Programming Operating Modes ............................................................................................ 497

23-1

Operand Identifiers and Description Methods ................................................................................... 504

A-1

Major Differences between

PD78014, 78014H, and 78018F Subseries ........................................ 521

B-1

System-up Method from Other In-Circuit Emulator to IE-78000-R ................................................... 532

B-2

System-up Method from Other In-Circuit Emulator to IE-78000-R-A ................................................ 532

Summary of Contents for 78011BGC AB8 Series

Page 1: ...ICROCONTROLLERS µPD78011B µPD78011BY µPD78012B µPD78012BY µPD78013 µPD78013Y µPD78014 µPD78014Y µPD78P014 µPD78P014Y µPD78011B A µPD78012B A µPD78013 A µPD78014 A User s Manual Printed in Japan Document No U10085EJ7V0UM00 7th edition Date Published October 1997 N 1992 ...

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Page 3: ...nection for CMOS device inputs can be cause of malfunction If no connection is provided to the input pins it is possible that an internal input level may be generated due to noise etc hence causing malfunction CMOS devices behave differently than Bipolar or NMOS devices Input levels of CMOS devices must be fixed high or low by using a pull up or pull down circuitry Each unused pin should be connec...

Page 4: ...ime Operating system Nucleus ITRON is an abbreviation of Industrial TRON License not needed µPD78P014DW 78P014YDW The customer must judge the need for license µPD78011BCW 78011BGC AB8 µPD78011BCW A 78011BGC A AB8 µPD78011BYCW 78011BYGC AB8 µPD78012BCW 78012BGC AB8 µPD78012BCW A 78012BGC A AB8 µPD78012BYCW 78012BYGC AB8 µPD78013CW 78013GC AB8 µPD78013CW A 78013GC A AB8 µPD78013YCW 78013YGC AB8 µPD7...

Page 5: ...y fire containment and anti failure features NEC devices are classified into the following three quality grades Standard Special and Specific The Specific quality grade applies only to devices developed based on a customer designated quality assurance program for a specific application The recommended applications of a device depend on its quality grade as indicated below Customers must check the ...

Page 6: ...oven The Netherlands Tel 040 2445845 Fax 040 2444580 NEC Electronics France S A Velizy Villacoublay France Tel 01 30 67 58 00 Fax 01 30 67 58 99 NEC Electronics France S A Spain Office Madrid Spain Tel 01 504 2787 Fax 01 504 2860 NEC Electronics Germany GmbH Scandinavia Office Taeby Sweden Tel 08 63 80 820 Fax 08 63 80 388 Regional Information Some information contained in this document may vary f...

Page 7: ...al Interface Channel 0 Control Register 2 Serial operating mode register 0 CSIM0 p 287 310 348 371 Cautions were added in sections 15 4 3 and 16 4 3 2 a Bus release signal REL b Command signal CMD 11 Cautions on SBI mode p 421 3 MSB LSB switching as the start bit was added in section 17 4 2 3 wire serial I O mode operation p 439 3 d Busy control option e Busy strobe control option and f Bit slippa...

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Page 9: ...s manual and Instructions common to the 78K 0 Series µPD78014 78014Y SUBSERIES 78K 0 SERIES USER S MANUAL USER S MANUAL This manual Instructions Pin functions CPU functions Internal block functions Instruction set Interrupts Explanation of each instruction Miscellaneous on chip peripheral functions How to Read This Manual Before reading this manual you must have general knowledge of electric and l...

Page 10: ...EU1372 For the electrical specifications of the µPD78014 78014Y Subseries Refer to Data Sheet For the application examples of µPD78014 78014Y Subseries functions Refer to Application Note Caution The use examples in the manual apply to the general electric devices of the standard quality grade To use the use examples in the manual for applications requiring the special quality grade examine the qu...

Page 11: ...ion µPD78014Y Subseries Chapter 5 CPU Architecture Chapter 6 Port Functions Chapter 7 Clock Generator Chapter 8 16 bit Timer Event Counter Chapter 9 8 bit Timer Event Counter Chapter 10 Watch Timer Chapter 11 Watchdog Timer Chapter 12 Clock Output Control Circuit Chapter 13 Buzzer Output Control Circuit Chapter 14 A D Converter Chapter 15 Serial Interface Channel 0 µPD78014 Subseries Chapter 16 Se...

Page 12: ...adecimal H Document Name Document Number Japanese Version English Version µPD78014 78014Y Subseries User s Manual U10085J This manual µPD78011B 78012B 78013 78014 Data Sheet IC 8201 IC 3179 µPD78P014 Data Sheet IC 8111 IC 3098 µPD78011B A 78012B A 78013 A 78014 A Data Sheet IC 8874 IC 3411 µPD78011BY 78012BY 78013Y 78014Y Data Sheet IC 8573 IC 3405 µPD78P014Y Data Sheet IC 8572 IC 3180 µPD78014 78...

Page 13: ... 805 EEU 1400 IE 78014 R EM A EEU 962 EEU 1487 EP 78240 EEU 986 U10332E SM78K0 System Simulator Windows Reference U10181J U10181E SM78 Series System Simulator External Part User U10092J U10092E Open Interface Specification ID79K0 Integrated Debugger EWS based Reference U11151J ID78K0 Integrated Debugger PC based Reference U11539J U11539E ID78K0 Integrated Debugger Windows based Guides U11649J U116...

Page 14: ...Semiconductor Devices C11531J C11531E Reliability and Quality Control of NEC Semiconductor Devices C10983J C10983E Electrostatic Discharge ESD Test MEM 539 Guide to Quality Assurance of Semiconductor Devices C11893J MEI 1202 Guide to Microcontroller Related Products Other Manufacturers U11416J Caution The contents of the above documents are subject to change without notice Be sure to use the lates...

Page 15: ...ds 50 2 3 Ordering Information 50 2 4 Quality Grade 50 2 5 Pin Configurations Top View 51 2 6 78K 0 Series Expansion 56 2 7 Block Diagram 58 2 8 Outline of Function 59 2 9 Mask Options 61 CHAPTER 3 PIN FUNCTION µPD78014 Subseries 63 3 1 Pin Function List 63 3 1 1 Normal operating mode pins 63 3 1 2 PROM programming mode pins µPD78P014 only 66 3 2 Description of Pin Functions 67 3 2 1 P00 to P04 Po...

Page 16: ...6 88 4 2 8 AVREF 88 4 2 9 AVDD 88 4 2 10 AVSS 88 4 2 11 RESET 88 4 2 12 X1 and X2 88 4 2 13 XT1 and XT2 89 4 2 14 VDD 89 4 2 15 VSS 89 4 2 16 VPP µPD78P014Y only 89 4 2 17 IC Mask ROM versions only 89 4 3 Input Output Circuit and Recommended Connection of Unused Pins 90 CHAPTER 5 CPU ARCHITECTURE 95 5 1 Memory Spaces 95 5 1 1 Internal program memory space 100 5 1 2 Internal data memory space 101 5...

Page 17: ... Port 6 144 6 3 Port Function Control Registers 146 6 4 Port Function Operations 152 6 4 1 Writing to input output port 152 6 4 2 Reading from input output port 152 6 4 3 Operations on input output port 153 6 5 Mask Options 154 CHAPTER 7 CLOCK GENERATOR 155 7 1 Clock Generator Functions 155 7 2 Clock Generator Configuration 155 7 3 Clock Generator Control Register 157 7 4 System Clock Oscillator 1...

Page 18: ...nter mode 202 9 2 8 Bit Timer Event Counter Configuration 204 9 3 8 Bit Timer Event Counter Control Registers 207 9 4 8 Bit Timer Event Counter Operations 212 9 4 1 8 bit timer event counter mode 212 9 4 2 16 bit timer event counter mode 216 9 5 Cautions on 8 Bit Timer Event Counter Operating 220 CHAPTER 10 WATCH TIMER 223 10 1 Watch Timer Functions 223 10 2 Watch Timer Configuration 224 10 3 Watc...

Page 19: ... 2 Serial Interface Channel 0 Configuration 267 15 3 Serial Interface Channel 0 Control Registers 271 15 4 Serial Interface Channel 0 Operations 277 15 4 1 Operation stop mode 277 15 4 2 3 wire serial I O mode operation 278 15 4 3 SBI mode operation 283 15 4 4 2 wire serial I O mode operation 310 15 4 5 SCK0 P27 pin output manipulation 317 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 µPD78014Y Subseries ...

Page 20: ... 2 Maskable interrupt request acknowledge operation 462 18 4 3 Software interrupt request acknowledge operation 465 18 4 4 Multiple interrupt servicing 465 18 4 5 Interrupt request reserve 468 18 5 Test Function 469 18 5 1 Test function control registers 469 18 5 2 Test input signal acknowledge operation 471 CHAPTER 19 EXTERNAL DEVICE EXPANSION FUNCTION 473 19 1 External Device Expansion Functions...

Page 21: ...ted by Addressing Type 516 APPENDIX A DIFFERENCES BETWEEN µPD78014 78014H AND 78018F SUBSERIES 521 APPENDIX B DEVELOPMENT TOOLS 523 B 1 Language Processing Software 525 B 2 PROM Programming Tools 526 B 2 1 Hardware 526 B 2 2 Software 526 B 3 Debugging Tools 527 B 3 1 Hardware 527 B 3 2 Software 528 B 4 OS for IBM PC 531 B 5 System up Method from Other In Circuit Emulator to In Circuit Emulator for...

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Page 23: ...18 5 16 Data Memory Addressing µPD78P014 78P014Y 119 6 1 Port Types 129 6 2 P00 Block Diagram 134 6 3 P01 to P03 Block Diagrams 135 6 4 P04 Block Diagram 135 6 5 P10 to P17 Block Diagrams 136 6 6 P20 P21 P23 to P26 Block Diagrams µPD78014 Subseries 137 6 7 P22 and P27 Block Diagrams µPD78014 Subseries 138 6 8 P20 P21 P23 to P26 Block Diagrams µPD78014Y Subseries 139 6 9 P22 and P27 Block Diagrams ...

Page 24: ...ter 190 8 15 Timing of Pulse Width Measurement Operation by Free Running Counter with Both Edges Specified 191 8 16 Timing of Pulse Width Measurement Operation by Means of Restart with Both Edges Specified 192 8 17 External Event Counter Configuration Diagram 193 8 18 External Event Counter Operation Timings with Rising Edge Specified 194 8 19 Square Wave Output Operation Timings 195 8 20 16 Bit T...

Page 25: ...rmat 246 14 1 A D Converter Block Diagram 248 14 2 A D Converter Mode Register Format 252 14 3 A D Converter Input Select Register Format 253 14 4 A D Converter Basic Operation 255 14 5 Relationship between Analog Input Voltage and A D Conversion Result 256 14 6 A D Conversion by Hardware Start 257 14 7 A D Conversion by Software Start 258 14 8 Example of Method of Reducing Power Dissipation in St...

Page 26: ...sion from Slave Device to Master Device 308 15 32 Example of Serial Bus Configuration with 2 Wire Serial I O 310 15 33 2 Wire Serial I O Mode Timings 315 15 34 RELT and CMDT Operations 316 15 35 SCK0 P27 Pin Configuration 317 16 1 Serial Bus Interface SBI System Configuration Example 322 16 2 Serial Bus Configuration Example with 2 Wire Serial I O 323 16 3 Serial Bus Configuration Example Using I2...

Page 27: ...rt Condition 380 16 39 Address 381 16 40 Transfer Direction Specification 381 16 41 Acknowledge Signal 382 16 42 Stop Condition 382 16 43 Wait Signal 383 16 44 Pin Configuration 391 16 45 Data Transmission from Master to Slave Both Master and Slave Selected 9 Clock Wait 393 16 46 Data Transmission from Slave to Master Both Master and Slave Selected 9 Clock Wait 396 16 47 Start Condition Output 400...

Page 28: ...Flag Register Format 453 18 4 Priority Specify Flag Register Format 454 18 5 External Interrupt Mode Register Format 455 18 6 Sampling Clock Select Register Format 456 18 7 Noise Eliminator Input Output Timing when rising edge is detected 457 18 8 Program Status Word Configuration 458 18 9 Flowchart from Non Maskable Interrupt Request Generation to Acknowledge 460 18 10 Non Maskable Interrupt Requ...

Page 29: ... upon RESET Input 490 21 1 Block Diagram of Reset Function 491 21 2 Timing of Reset by RESET Input 492 21 3 Timing of Reset due to Watchdog Timer Overflow 492 21 4 Timing of Reset in STOP Mode by RESET Input 492 22 1 Internal Memory Size Switching Register Format 496 22 2 PROM Write Verify Timing 498 22 3 Write Procedure Flowchart 499 22 4 PROM Read Timing 500 B 1 Development Tools Configuration 5...

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Page 31: ...Instruction Execution Time 159 7 3 Maximum Time Required for CPU Clock Switchover 168 8 1 Timer Event Counter Operation 172 8 2 16 Bit Timer Event Counter Interval Times 172 8 3 16 Bit Timer Event Counter Square Wave Output Ranges 173 8 4 16 Bit Timer Event Counter Configuration 173 8 5 16 Bit Timer Event Counter Interval Times 187 8 6 16 Bit Timer Event Counter Square Wave Output Ranges 195 9 1 8...

Page 32: ...onfiguration 267 15 4 Various Signals in SBI Mode 300 16 1 Differences between Channels 0 and 1 319 16 2 Difference of Serial Interface Channel 0 Mode 320 16 3 Serial Interface Channel 0 Configuration 325 16 4 Serial Interface Channel 0 Interrupt Request Signal Generation 329 16 5 Various Signals in SBI Mode 361 16 6 Signals in the I2C Bus Mode 390 17 1 Serial Interface Channel 1 Configuration 410...

Page 33: ...set 493 22 1 Differences between µPD78P014 78P014Y and Mask ROM Version 495 22 2 Internal Memory Size Switching Register Value at Reset 496 22 3 PROM Programming Operating Modes 497 23 1 Operand Identifiers and Description Methods 504 A 1 Major Differences between µPD78014 78014H and 78018F Subseries 521 B 1 System up Method from Other In Circuit Emulator to IE 78000 R 532 B 2 System up Method fro...

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Page 35: ...10 0 MHz with main system clock to ultra low speed 122 µs 32 768 KHz with subsystem clock Instruction set suitable for system control Bit manipulation can be enabled in all the address space Multiplication division instruction 53 I O ports N ch open drain 4 8 bit resolution A D converter 8 channels Low voltage operation AVDD 2 7 to 6 0 V operable at the same voltage range as CPU Serial interface 2...

Page 36: ...750 mils Mask ROM µPD78013GC AB8 64 pin plastic QFP 14 14 mm Mask ROM µPD78014CW 64 pin plastic shrink DIP 750 mils Mask ROM µPD78014GC AB8 64 pin plastic QFP 14 14 mm Mask ROM µPD78P014CW 64 pin plastic shrink DIP 750 mils One time PROM µPD78P014DW 64 pin ceramic shrink DIP with window 750 mils EPROM µPD78P014GC AB8 64 pin plastic QFP 14 14 mm One time PROM µPD78011BCW A 64 pin plastic shrink DIP...

Page 37: ...14GC AB8 64 pin plastic QFP 14 14 mm Standard µPD78011BCW A 64 pin plastic shrink DIP 750 mils Special µPD78011BGC AB8 64 pin plastic QFP 14 14 mm Special µPD78012BCW A 64 pin plastic shrink DIP 750 mils Special µPD78012BGC A AB8 64 pin plastic QFP 14 14 mm Special µPD78013CW A 64 pin plastic shrink DIP 750 mils Special µPD78013GC A AB8 64 pin plastic QFP 14 14 mm Special µPD78014CW A 64 pin plast...

Page 38: ...e µPD78P014 P20 SI1 P21 SO1 P22 SCK1 P23 STB P24 BUSY P25 SI0 SB0 P26 SO0 SB1 P27 SCK0 P30 TO0 P31 TO1 P32 TO2 P33 TI1 P34 TI2 P35 PCL P36 BUZ P37 VSS P40 AD0 P41 AD1 P42 AD2 P43 AD3 P44 AD4 P45 AD5 P46 AD6 P47 AD7 P50 A8 P51 A9 P52 A10 P53 A11 P54 A12 P55 A13 VSS 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ...

Page 39: ... 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P47 AD7 P50 A8 P51 A9 P52 A10 P53 A11 P54 A12 P55 A13 V SS P56 A14 P57 A15 P60 P61 P62 P63 P64 RD P65 WR 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P30 TO0 P31 TO1 P32 TO2 P33 TI1 P34 TI2 P35 PCL P36 BUZ P37 VSS P40 AD0 P41 AD1 P42 AD2 P43 AD3 P44 AD4 P45 AD5 P46 AD6 P11 ANI1 P10 ANI0 AVSS P04 XT1 XT2 IC VPP X1 X2 VDD P03 INTP3 P02 INTP2 ...

Page 40: ...Strobe X1 X2 Crystal Main System Clock XT1 XT2 Crystal Subsystem Clock A8 to A15 Address Bus AD0 to AD7 Address Data Bus ANI0 to ANI7 Analog Input ASTB Address Strobe AVDD Analog Power Supply AVREF Analog Reference Voltage AVSS Analog Ground BUSY Busy BUZ Buzzer Clock IC Internally Connected INTP0 to INTP3 Interrupt from Peripherals P00 to P04 Port0 P10 to P17 Port1 P20 to P27 Port2 P30 to P37 Por...

Page 41: ...ia a pull down resistor 2 VSS Connect to the ground 3 RESET Set to the low level 4 Open No connection required D0 D1 D2 D3 D4 D5 D6 D7 VSS A0 A1 A2 A3 A4 A5 A6 A7 A8 A10 A11 A12 A13 VSS 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VSS VDD VSS Open VPP Open VDD A9 R...

Page 42: ... A14 Address Bus RESET Reset CE Chip Enable VDD Power Supply D0 to D7 Data Bus VPP Programming Power Supply OE Output Enable VSS Ground 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 A7 A8 L A10 A11 A12 A13 V SS A14 OE CE 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 D0 D1 D2 D3 D4 D5 D6 D7 VSS A0 A1 A2 A3 A4 A5 A6 VSS VPP VDD A9 RESET 64 63 62 61 60 59 58...

Page 43: ...D78098 80 pin PD78P0914 64 pin 78K 0 Series An N ch open drain I O was added to the PD78044F Display output total 34 Basic subseries for driving FIP Display output total 34 LCD drive The SIO of the PD78064 was enhanced and ROM RAM capacity increased EMI noise reduced version of the PD78064 Basic subseries for driving LCDs On chip UART IEBus supported An IEBus controller was added to the PD78054 LV...

Page 44: ...me division µPD780024 8ch 3 wire 1ch µPD78014H 2ch 53 1 8 V µPD78018F 8K to 60K µPD78014 8K to 32K 2 7 V µPD780001 8K 1ch 39 µPD78002 8K to 16K 1ch 53 µPD78083 8ch 1ch UART 1ch 33 1 8 V Inverter µPD780964 8K to 32K 3ch Note 1ch 8ch 2ch UART 2ch 47 2 7 V control µPD780924 8ch FIP µPD780208 32K to 60K 2ch 1ch 1ch 1ch 8ch 2ch 74 2 7 V drive µPD780228 48K to 60K 3ch 1ch 72 4 5 V µPD78044H 32K to 48K 2...

Page 45: ... AVDD AVSS AVREF INTP0 P00 to INTP3 P03 BUZ P36 CLOCK OUTPUT CONTROL PCL P35 BUZZER OUTPUT INTERRUPT CONTROL A D CONVERTER SERIAL INTERFACE 1 SERIAL INTERFACE 0 WATCH TIMER WATCHDOG TIMER 8 bit TIMER EVENT COUNTER 2 8 bit TIMER EVENT COUNTER 1 16 bit TIMER EVENT COUNTER 78K 0 CPU CORE ROM RAM VDD VSS SYSTEM CONTROL EXTERNAL ACCESS PORT6 PORT5 PORT4 PORT3 PORT2 PORT1 PORT0 P00 P01 to P03 P04 P10 to...

Page 46: ...n set reset test and Boolean operation BCD adjust and other related operations I O ports Total 53 I O port pins CMOS input 2 inputs CMOS I O 47 inputs outputs on chip pull up resistor can be turned on off by software N ch open drain I O 4 inputs outputs 15 V withstand on chip pull up resistor with mask options in mask ROM versions only A D converter 8 bit resolution 8 channels Low voltage operatio...

Page 47: ... 313 kHz 625 kHz 1 25 MHz 10 0 MHz with main system clock 32 768 kHz 32 768 kHz with subsystem clock Buzzer output 2 4 kHz 4 9 kHz 9 8 kHz 10 0 MHz with main system clock Vectored Maskable Internal 8 external 4 interrupt Non maskable Internal 1 sources Software 1 Test input Internal 1 external 1 Power supply voltage VDD 2 7 to 6 0 V Operating ambient temperature TA 40 to 85 C Package 64 pin plasti...

Page 48: ...3 µPD78014 have the mask options By specifying the mask options when ordering the pull up resistors and pull down resistors listed in Table 1 2 can be incorporated When these resistors are necessary the number of external components and mounting space can be saved by utilizing the mask options Mask options provided in the µPD78014 Subseries are shown in Table 1 2 Table 1 2 Mask Options in Mask ROM...

Page 49: ...z with main system clock to ultra low speed 122 µs 32 768 kHz with subsystem clock Instruction set suitable for system control Bit manipulation enable in all the address space Multiplication division instruction 53 I O ports N ch open drain 4 8 bit resolution A D converter 8 channels Low voltage operation AVDD 2 7 to 6 0 V operable at the same supply voltage range as CPU Serial interface 2 channel...

Page 50: ...Quality Grade µPD78011BYCW 64 pin plastic shrink DIP 750 mils Standard µPD78011BYGC AB8 64 pin plastic QFP 14 14 mm Standard µPD78012BYCW 64 pin plastic shrink DIP 750 mils Standard µPD78012BYGC AB8 64 pin plastic QFP 14 14 mm Standard µPD78013YCW 64 pin plastic shrink DIP 750 mils Standard µPD78013YGC AB8 64 pin plastic QFP 14 14 mm Standard µPD78014YCW 64 pin plastic shrink DIP 750 mils Standard...

Page 51: ... P22 SCK1 P23 STB P24 BUSY P25 SI0 SB0 SDA0 P26 SO0 SB1 SDA1 P27 SCK0 SCL P30 TO0 P31 TO1 P32 TO2 P33 TI1 P34 TI2 P35 PCL P36 BUZ P37 VSS P40 AD0 P41 AD1 P42 AD2 P43 AD3 P44 AD4 P45 AD5 P46 AD6 P47 AD7 P50 A8 P51 A9 P52 A10 P53 A11 P54 A12 P55 A13 VSS 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 2...

Page 52: ... 38 37 36 35 34 33 P47 AD7 P50 A8 P51 A9 P52 A10 P53 A11 P54 A12 P55 A13 V SS P56 A14 P57 A15 P60 P61 P62 P63 P64 RD P65 WR 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P30 TO0 P31 TO1 P32 TO2 P33 TI1 P34 TI2 P35 PCL P36 BUZ P37 VSS P40 AD0 P41 AD1 P42 AD2 P43 AD3 P44 AD4 P45 AD5 P46 AD6 P11 ANI1 P10 ANI0 AVSS P04 XT1 XT2 IC VPP X1 X2 VDD P03 INTP3 P02 INTP2 P01 INTP1 P00 INTP0 TI0 RESET P67 AS...

Page 53: ...P17 Port1 P20 to P27 Port2 P30 to P37 Port3 P40 to P47 Port4 P50 to P57 Port5 P60 to P67 Port6 PCL Programmable Clock RD Read Strobe RESET Reset SB0 SB1 Serial Bus SCK0 SCK1 Serial Clock SCL Serial Clock SDA0 SDA1 Serial Data SI0 SI1 Serial Input SO0 SO1 Serial Output STB Strobe TI0 to TI2 Timer Input TO0 to TO2 Timer Output VDD Power Supply VPP Programming Power Supply VSS Ground WAIT Wait WR Wri...

Page 54: ... via a pull down resistor 2 VSS Connect to the ground 3 RESET Set to the low level 4 Open No connection required L D0 D1 D2 D3 D4 D5 D6 D7 VSS A0 A1 A2 A3 A4 A5 A6 A7 A8 L A10 A11 A12 A13 VSS 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VSS VDD VSS L Open VPP Open ...

Page 55: ...A14 Address Bus RESET Reset CE Chip Enable VDD Power Supply D0 to D7 Data Bus VPP Programming Power Supply OE Output Enable VSS Ground 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 A7 A8 A10 A11 A12 A13 V SS A14 OE CE 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 D0 D1 D2 D3 D4 D5 D6 D7 VSS A0 A1 A2 A3 A4 A5 A6 VSS VPP VDD A9 RESET 64 63 62 61 60 59 58 57...

Page 56: ...PD78098 80 pin PD78P0914 64 pin 78K 0 Series An N ch open drain I O was added to the PD78044F Display output total 34 Basic subseries for driving FIP Display output total 34 LCD drive The SIO of the PD78064 was enhanced and ROM RAM capacity increased EMI noise reduced version of the PD78064 Basic subseries for driving LCDs On chip UART IEBus supported An IEBus controller was added to the PD78054 L...

Page 57: ... transmit receive function 1ch 3 wire time division UART 1ch µPD78058FY 48K to 60K 3 wire 2 wire I2 C 1ch 69 2 7 V 3 wire with automatic transmit receive function 1ch µPD78054Y 16K to 60K 3 wire UART 1ch 2 0 V µPD780034Y 8K to 32K UART 1ch 51 1 8 V 3 wire 1ch µPD780024Y I2 C bus supports multi master 1ch µPD78018FY 8K to 60K 3 wire 2 wire I2 C 1ch 53 3 wire with automatic transmit receive function...

Page 58: ...ANI7 P17 AVDD AVSS AVREF INTP0 P00 to INTP3 P03 BUZ P36 CLOCK OUTPUT CONTROL PCL P35 BUZZER OUTPUT INTERRUPT CONTROL A D CONVERTER SERIAL INTERFACE 1 SERIAL INTERFACE 0 WATCH TIMER WATCHDOG TIMER 8 bit TIMER EVENT COUNTER 2 8 bit TIMER EVENT COUNTER 1 16 bit TIMER EVENT COUNTER 78K 0 CPU CORE ROM RAM VDD VSS IC VPP SYSTEM CONTROL EXTERNAL ACCESS PORT6 PORT5 PORT4 PORT3 PORT2 PORT1 PORT0 P00 P01 to...

Page 59: ...on set reset test and Boolean operation BCD adjust and other related operations I O ports Total 53 I O ports CMOS input 2 inputs CMOS I O 47 inputs outputs on chip pull up resistor can be turn on off by software N ch open drain I O 4 inputs outputs 15 V withstand on chip pull up resistor with mask options in mask ROM versions only A D converter 8 bit resolution 8 channels Low voltage operation AVD...

Page 60: ...with main system clock 32 768 kHz 32 768 kHz with subsystem clock Buzzer output 2 4 kHz 4 9 kHz 9 8 kHz 10 0 MHz with main system clock Vectored Maskable Internal 8 external 4 interrupt Non maskable Internal 1 sources Software 1 Test input Internal 1 external 1 Power supply voltage VDD 2 7 to 6 0 V Operating ambient temperature TA 40 to 85 C Package 64 pin plastic shrink DIP 750 mil 64 pin plastic...

Page 61: ...e pull up resistors and pull down resistors listed in Table 2 1 can be incorporated When these resistors are necessary the number of external components and mounting space can be saved by utilizing the mask options Mask options provided in the µPD78014Y subseries are shown in Table 2 1 Table 2 1 Mask Options in Mask ROM Versions Pin Name Mask Option P60 to P63 Pull up resistors can be incorporated...

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Page 63: ...istor can be connected by softwareNote 2 P20 Input Port 2 Input SI1 P21 Output 8 bit input output port SO1 P22 Input output specifiable bit wise SCK1 P23 If used as an input port an on chip pull up resistor can be connected STB P24 by software BUSY P25 SI0 SB0 P26 SO0 SB1 P27 SCK0 P30 Input Port 3 Input TO0 P31 Output 8 bit input output port TO1 P32 LED can be driven directly TO2 P33 Input output ...

Page 64: ...alling edge detection P50 to P57 Input Port 5 Input A8 to A15 Output 8 bit input output port Input output specifiable in 8 bit wise LED can be driven directly When used as an input port an on chip pull up resistor can be connected by software P60 Input Port 6 N ch open drain input output port Input P61 Output 8 bit input output port On chip pull up resistor can be P62 Input output specifiable bit ...

Page 65: ...terface automatic transmit receive busy input Input P24 TI0 Input External count clock input to 16 bit timer TM0 Input P00 INTP0 TI1 External count clock input to 8 bit timer TM1 P33 TI2 External count clock input to 8 bit timer TM2 P34 TO0 Output 16 bit timer TM0 output also used for 14 bit PWM output Input P30 TO1 8 bit timer TM1 output P31 TO2 8 bit timer TM2 output P32 PCL Output Clock output ...

Page 66: ...XT2 VDD Positive power supply VPP High voltage application for program write verify Connect directly to VSS in normal operating mode VSS Ground potential IC Internally connected Connect directly to VSS 3 1 2 PROM programming mode pins µPD78P014 only Pin Name Input Function Output RESET Input PROM programming mode setting When 5 V or 12 5 V is applied to the VPP pin or a low level voltage is applie...

Page 67: ... register 0 PM0 When they are used as input ports a pull up resistor can be connected to them with an on chip pull up resistor option register PUO 2 Control mode In this mode these ports function as an external interrupt request input an external count clock input to the timer and crystal connection for subsystem clock oscillation a INTP0 to INTP3 INTP0 to INTP2 are external interrupt request inpu...

Page 68: ...ise 1 Port mode These ports function as 8 bit input output ports They can be specified bit wise as input or output ports with port mode register 1 PM1 When used as an input port an on chip pull up resistor can be connected to these ports with a pull up resistor option register PUO 2 Control mode These ports function as A D converter analog input pins ANI0 to ANI7 If the pins are specified as analo...

Page 69: ...them with a pull up resistor option register PUO 2 Control mode These ports function as serial interface data input output clock input output automatic transmit receive busy input and strobe output a SI0 SI1 SO0 SO1 Serial interface serial data input output pins b SCK0 and SCK1 Serial interface serial clock input output pins c SB0 and SB1 NEC standard serial bus interface input output pins d BUSY ...

Page 70: ... ports function as 8 bit input output ports They can be specified bit wise as input or output ports with port mode register 3 PM3 When they are used as input ports an on chip pull up resistor can be connected with a pull up resistor option register PUO 2 Control mode These ports function as timer input output clock output and buzzer output a TI1 and TI2 Pins for external count clock input to the 8...

Page 71: ... as low order address data bus pins in external memory expansion mode When they are used as address data bus an on chip pull up resistor is automatically unused 3 2 6 P50 to P57 Port 5 These are 8 bit input output ports Besides serving as input output ports they function as address data bus They can drive LEDs directly The following operating modes can be specified bit wise 1 Port mode These ports...

Page 72: ...se ports function as control signal output pins RD WR WAIT ASTB in external memory expansion mode When a pin is used as control signal output the on chip pull up resistor is automatically disabled Caution When external wait is not used in external memory expansion mode P66 can be used as an input output port 3 2 8 AVREF A D converter reference voltage input pin When the A D converter is not used c...

Page 73: ...am write verify Connect directly to VSS in normal operating mode 3 2 17 IC Mask ROM version only The IC Internally Connected pin sets a test mode in which the µPD78011B 78012B 78013 and 78014 are tested before shipment In normal operation mode connect the IC pin directly to VSS with as short a wiring length as possible If there is a potential difference between the IC and VSS pins because the wiri...

Page 74: ...put output Independently connect to VSS via a resistor P02 INTP2 P03 INTP3 P04 XT1 16 Input Connect to VDD or VSS P10 ANI0 to P17 ANI7 11 Input output Independently connect to VDD or VSS via a resistor P20 SI1 8 A P21 SO1 5 A P22 SCK1 8 A P23 STB 5 A P24 BUSY 8 A P25 SI0 SB0 10 A P26 SO0 SB1 P27 SCK0 P30 TO0 5 A P31 TO1 P32 TO2 P33 TI1 8 A P34 TI2 P35 PCL 5 A P36 BUZ P37 P40 AD0 to P47 AD7 5 E Ind...

Page 75: ... Pin Input Output Circuit Types 2 2 Pin Name Input Output Input Output Recommended Connection for Unused Pins Circuit Type RESET 2 Input XT2 16 Leave open AVREF Connect to VSS AVDD Connect to VDD AVSS Connect to VSS IC Mask ROM Version Connect directly to VSS VPP PROM Version ...

Page 76: ...pull up enable data output disable VDD P ch N ch P ch IN OUT VDD Type 5 A input enable Type 5 E pull up enable data output disable VDD P ch N ch P ch IN OUT VDD Schmitt triggered input with hysteresis characteristics pull up enable data open drain output disable N ch P ch VDD VDD P ch IN OUT pull up enable data output disable input enable N ch VDD P ch IN OUT VDD P ch P ch N ch VREF threshold volt...

Page 77: ... 77 Figure 3 1 Pin Input Output Circuit List 2 2 Type 13 Type 16 Type 13 B data output disable N ch IN OUT VDD VDD RD Mask Option Middle High Voltage Input Buffer XT1 XT2 P ch feedback cut off P ch data output disable N ch IN OUT Middle High Voltage Input Buffer ...

Page 78: ...www DataSheet4U com CHAPTER 3 PIN FUNCTION µPD78014 Subseries 78 MEMO ...

Page 79: ...pull up resistor can be connected by softwareNote 2 P20 Input Port 2 Input SI1 P21 Output 8 bit input output port SO1 P22 Input output specifiable bit wise SCK1 P23 If used as an input port an on chip pull up resistor can be connected by STB P24 software BUSY P25 SI0 SB0 SDA0 P26 SO0 SB1 SDA1 P27 SCK0 SC1 P30 Input Port 3 Input TO0 P31 Output 8 bit input output port TO1 P32 Input output specifiabl...

Page 80: ...by falling edge detection P50 to P57 Input Port 5 Input A8 to A15 Output 8 bit input output port LED can be driven directly Input output specifiable bit wise When used as an input port an on chip pull up resistor can be connected by software P60 Input Port 6 N ch open drain input output port Input P61 Output 8 bit input output port On chip pull up resistor can be P62 Input output specifiable bit w...

Page 81: ...utput Input P23 BUSY Input Serial interface automatic transmit receive busy input Input P24 TI0 Input External count clock input to 16 bit timer TM0 Input P00 INTP0 TI1 External count clock input to 8 bit timer TM1 P33 TI2 External count clock input to 8 bit timer TM2 P34 TO0 Output 16 bit timer TM0 output also used for 14 bit PWM output Input P30 TO1 8 bit timer TM1 output P31 TO2 8 bit timer TM2...

Page 82: ...XT2 VDD Positive power supply VPP High voltage application for program write verify Connect directly to VSS in normal operating mode VSS Ground potential IC Internally connected Directly connect to VSS 4 1 2 PROM programming mode pins µPD78P014Y only Pin Name Input Function Output RESET Input PROM programming mode setting When 5 V or 12 5 V is applied to the VPP pin or a low level voltage is appli...

Page 83: ...e register 0 PM0 When they are used as input ports a pull up resistor can be connected to them with an on chip pull up resistor option register PUO 2 Control mode In this mode these ports function as an external interrupt request input an external count clock input to the timer and crystal connection for subsystem clock oscillation a INTP0 to INTP3 INTP0 to INTP2 are external interrupt request inp...

Page 84: ... wise 1 Port mode These ports function as 8 bit input output ports They can be specified bit wise as input or output ports with port mode register 1 PM1 When used as input ports an on chip pull up resistor can be connected to these ports with a pull up resistor option register PUO 2 Control mode These ports function as A D converter analog input pins ANI0 to ANI7 If the pins are specified as analo...

Page 85: ...a pull up resistor option register PUO 2 Control mode These ports function as serial interface data input output clock input output automatic transmit receive busy input and strobe output a SI0 SI1 SO0 SO1 SDA0 SDA1 Serial interface serial data input output pins b SCK0 SCK1 SCL Serial interface serial clock input output pins c SB0 and SB1 NEC standard serial bus interface input output pins d BUSY ...

Page 86: ...e ports function as 8 bit input output ports They can be specified bit wise as input or output ports with port mode register 3 PM3 When they are used as input ports an on chip pull up resistor can be connected with a pull up resistor option register PUO 2 Control mode These ports function as timer input output clock output and buzzer output a TI1 and TI2 Pins for external count clock input to the ...

Page 87: ...w order address data bus pins in external memory expansion mode When they are used as address data bus the on chip pull up resistor is automatically disabled 4 2 6 P50 to P57 Port 5 These are 8 bit input output ports Besides serving as input output ports they function as address data bus They can drive LEDs directly The following operating modes can be specified bit wise 1 Port mode These ports fu...

Page 88: ... ports function as control signal output pins RD WR WAIT ASTB in external memory expansion mode When a pin is used as control signal output the on chip pull up resistor is automatically disabled Caution When external wait is not used in external memory expansion mode P66 can be used as an input output port 4 2 8 AVREF A D converter reference voltage input pin When the A D converter is not used con...

Page 89: ...m write verify Connect directly to VSS in normal operating mode 4 2 17 IC Mask ROM versions only The IC Internally Connected pin sets a test mode in which the µPD78011BY 78012BY 78013Y and 78014Y are tested before shipment In normal operation mode connect the IC pin directly to VSS with as short a wiring length as possible If there is a potential difference between the IC and VSS pins because the ...

Page 90: ...put Independently connect to VSS via a resistor P02 INTP2 P03 INTP3 P04 XT1 16 Input Connect to VDD or VSS P10 ANI0 to P17 ANI7 11 Input output Independently connect to VDD or VSS via a resistor P20 SI1 8 A P21 SO1 5 A P22 SCK1 8 A P23 STB 5 A P24 BUSY 8 A P25 SI0 SB0 SDA0 10 A P26 SO0 SB1 SDA1 P27 SCK0 SCL P30 TO0 5 A P31 TO1 P32 TO2 P33 TI1 8 A P34 TI2 P35 PCL 5 A P36 BUZ P37 P40 AD0 to P47 AD7 ...

Page 91: ... Pin Input Output Circuit Types 2 2 Pin Name Input Output Input Output Recommended Connection for Unused Pins Circuit Type RESET 2 Input XT2 16 Leave open AVREF Connect to VSS AVDD Connect to VDD AVSS Connect to VSS IC Mask ROM Version Connect directly to VSS VPP PROM Version ...

Page 92: ...pull up enable data output disable VDD P ch N ch P ch IN OUT VDD Type 5 A input enable Type 5 E pull up enable data output disable VDD P ch N ch P ch IN OUT VDD Schmitt triggered input with hysteresis characteristics pull up enable data open drain output disable N ch P ch VDD VDD P ch IN OUT pull up enable data output disable input enable N ch VDD P ch IN OUT VDD P ch P ch N ch VREF threshold volt...

Page 93: ...s 93 Figure 4 1 Pin Input Output Circuit List 2 2 Type 13 Type 16 Type 13 B data output disable N ch IN OUT VDD VDD RD Mask Option Middle High Voltage Input Buffer XT1 XT2 P ch feedback cut off P ch data output disable N ch IN OUT Middle High Voltage Input Buffer ...

Page 94: ...www DataSheet4U com CHAPTER 4 PIN FUNCTION µPD78014Y Subseries 94 MEMO ...

Page 95: ...ited Buffer RAM 32 8 bits Use Prohibited External Memory 55936 8 bits Internal ROM 8192 8 bits Data Memory Space Program Memory Space Program Area CALLF Entry Area Program Area CALLT Table Area Vector Table Area Special Function Registers SFR 256 8 bits General Registers 32 8 bits Internal High Speed RAM 512 8 bits FF00H FEFFH FEE0H FEDFH FFFFH FD00H FCFFH FAE0H FADFH FA80H FA7FH 2000H 1FFFH 0000H...

Page 96: ...84 8 bits Data Memory Space Program Memory Space Program Area CALLF Entry Area Program Area CALLT Table Area Vector Table Area Special Function Registers SFR 256 8 bits General Registers 32 8 bits Internal High Speed RAM 512 8 bits FF00H FEFFH FEE0H FEDFH FFFFH FD00H FCFFH FAE0H FADFH FA80H FA7FH 4000H 3FFFH 0000H 0000H 0040H 003FH 0080H 007FH 0800H 07FFH 1000H 0FFFH 3FFFH FAC0H FABFH ...

Page 97: ...6 8 bits Data Memory Space Program Memory Space Program Area CALLF Entry Area Program Area CALLT Table Area Vector Table Area Special Function Registers SFR 256 8 bits General Registers 32 8 bits Internal High Speed RAM 1024 8 bits FF00H FEFFH FEE0H FEDFH FFFFH FB00H FAFFH FAE0H FADFH FA80H FA7FH 6000H 5FFFH 0000H 0000H 0040H 003FH 0080H 007FH 0800H 07FFH 1000H 0FFFH 5FFFH FAC0H FABFH ...

Page 98: ...8 8 bits Data Memory Space Program Memory Space Program Area CALLF Entry Area Program Area CALLT Table Area Vector Table Area Special Function Registers SFR 256 8 bits General Registers 32 8 bits Internal High Speed RAM 1024 8 bits FF00H FEFFH FEE0H FEDFH FFFFH FB00H FAFFH FAE0H FADFH FA80H FA7FH 8000H 7FFFH 0000H 0000H 0040H 003FH 0080H 007FH 0800H 07FFH 1000H 0FFFH 7FFFH FAC0H FABFH ...

Page 99: ...68 8 bits Data Memory Space Program Memory Space Program Area CALLF Entry Area Program Area CALLT Table Area Vector Table Area Special Function Registers SFR 256 8 bits General Registers 32 8 bits Internal High Speed RAM 1024 8 bits FF00H FEFFH FEE0H FEDFH FFFFH FB00H FAFFH FAE0H FADFH FA80H FA7FH 8000H 7FFFH 0000H 0000H 0040H 003FH 0080H 007FH 0800H 07FFH 1000H 0FFFH 7FFFH FAC0H FABFH ...

Page 100: ... 003FH is reserved as vector table area The RESET input and program start addresses for branch upon generation of each interrupt request are stored in the vector table area Of the 16 bit address the low order 8 bits are stored at even addresses and the high order 8 bits are stored at odd addresses Table 5 2 Vector Table Vector Table Address Interrupt Source Vector Table Address Interrupt Source 00...

Page 101: ... a stack memory area 2 Buffer RAM Buffer RAM is allocated to the 32 byte area from FAC0H to FADFH Buffer RAM is used for storing transmit receive data of serial interface channel 1 3 wire serial I O mode with automatic transmit receive function When not used in the 3 wire serial I O mode with automatic transmit receive function buffer RAM can also be used as normal RAM 5 1 3 Special function regis...

Page 102: ...ruction to be fetched When a branch instruction is executed immediate data and register contents are set RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter Figure 5 6 Program Counter Configuration 15 0 PC PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 2 Program status word PSW The program status word is an 8 bit register consis...

Page 103: ...t flags to select one of the four register banks In these flags the 2 bit information which indicates the register bank selected by SEL RBn instruction execution is stored d Auxiliary carry flag AC If the operation result has a carry from bit 3 or a borrow at bit 3 this flag is set to 1 It is reset to 0 in all other cases e In service priority flag ISP This flag manages the priority of acknowledge...

Page 104: ...Y FD00H to FEFFH µPD78013 78013Y 78014 78014Y 78P014 78P014Y FB00H to FEFFH Figure 5 8 Stack Pointer Configuration The SP is decremented ahead of write save to the stack memory and is incremented after read reset from the stack memory Each stack operation saves resets data as shown in Figures 5 9 and 5 10 Caution Since SP contents will be undefined by RESET input be sure to initialize the SP befor...

Page 105: ...on PC7 to PC0 PC15 to PC8 RET Instruction Register Pair Lower Register Pair Upper POP rp Instruction SP SP 1 SP SP 2 SP SP 1 SP SP 2 SP SP 1 SP 2 SP SP 3 PC7 to PC0 PC15 to PC8 PSW Interrupt and BRK Instruction SP SP 3 SP 3 SP 2 SP 1 SP PC7 to PC0 PC15 to PC8 CALL CALLF and CALLT Instruction SP SP 2 SP 2 SP 1 SP Register Pair Lower Register Pair Upper PUSH rp Instruction SP SP 2 SP 2 SP 1 SP ...

Page 106: ...ontrol instruction SEL RBn Because of the 4 register bank configuration an efficient program can be created by switching between a register for normal processing and a register for interrupt request for each bank Table 5 4 Absolute Address Corresponding to General Registers Bank Register Absolute Bank Register Absolute Name Function Absolute Address Name Function Absolute Address Name Name Name Na...

Page 107: ...R1 R0 8 Bit Processing 16 Bit Processing RP3 RP2 RP1 RP0 BANK0 BANK1 BANK2 BANK3 15 0 7 0 F E F F H F E F 8 H F E F 7 H F E F 0 H F E E F H F E E 8 H F E E 7 H F E E 0 H H L D E B C A X HL DE BC AX BANK0 BANK1 BANK2 BANK3 15 0 7 0 8 Bit Processing 16 Bit Processing F E F F H F E F 8 H F E F 7 H F E F 0 H F E E F H F E E 8 H F E E 7 H F E E 0 H ...

Page 108: ...n instruction operand sfr This manipulation can also be specified with an address 16 bit manipulation Describes the symbol reserved with assembler for the 16 bit manipulation instruction operand sfrp When addressing an address describe an even address Table 5 5 gives a list of special function registers The meaning of items in the table is as follows Symbols A symbol indicates an address of the sp...

Page 109: ...timer register 2 TM2 FF1AH Serial I O shift register 0 SIO0 R W Undefined FF1BH Serial I O shift register 1 SIO1 FF1FH A D conversion result register ADCR R FF20H Port mode register 0 PM0 R W 1FH FF21H Port mode register 1 PM1 FFH FF22H Port mode register 2 PM2 FF23H Port mode register 3 PM3 FF25H Port mode register 5 PM5 FF26H Port mode register 6 PM6 FF40H Timer clock select register 0 TCL0 00H ...

Page 110: ...ode register 1 CSIM1 FF69H Automatic data transmit receive control register ADTC FF6AH Automatic data transmit receive address pointer ADTP FF80H A D converter mode register ADM 01H FF84H A D converter input select register ADIS 00H FFD0H External access areaNote 1 Undefined to FFDFH FFE0H Interrupt request flag register 0L IF0 IF0L 00H FFE1H Interrupt request flag register 0H IF0H FFE4H Interrupt...

Page 111: ...1 Relative addressing Function The value obtained by adding 8 bit immediate data displacement value jdisp8 of an instruction code to the start address of the following instruction is transferred to the program counter PC and branched The displacement value is treated as signed two s complement data 128 to 127 and bit 7 becomes a sign bit In other words the range of branch in relative addressing is...

Page 112: ...the CALL addr16 BR addr16 or CALLF addr11 instruction is executed CALL addr16 and BR addr16 instructions can branch to all the memory spaces CALLF addr11 instruction branches to the area from 0800H to 0FFFH Illustration In the case of CALL addr16 and BR addr16 instructions In the case of CALLF addr11 instruction 7 0 High Addr PC 15 0 8 7 CALL or BR Low Addr 7 0 fa7 0 PC 15 0 6 4 3 11 10 8 7 0 0 0 ...

Page 113: ...ode are transferred to the program counter PC and branched Table indirect addressing is carried out when the CALLT addr5 instruction is executed This instruction can refer to the address stored in the memory table 40H to 7FH and branch to all the memory spaces Illustration 7 0 High Addr PC 15 0 8 7 Low Addr Effective Address 15 0 8 7 Operation Code 7 0 0 0 0 0 0 0 0 0 1 0 6 5 1 1 ta4 0 1 Memory Ta...

Page 114: ...Register addressing Function Register pair AX contents to be specified with an instruction word are transferred to the program counter PC and branched This function is carried out when the BR AX instruction is executed Illustration rp 7 0 A X 0 7 PC 15 0 8 7 ...

Page 115: ...lity In particular specific types of addressing can be used which match the functions of the special function registers SFRs general registers etc Data memory addressing is shown in Figures 5 12 to 5 16 Figure 5 12 Data Memory Addressing µPD78011B 78011BY Special Function Registers SFR 256 8 bits Internal High Speed RAM 512 8 bits General Registers 32 8 bits Use Prohibited Buffer RAM 32 8 bits Use...

Page 116: ... RAM 32 8 bits Use Prohibited External Memory 47744 8 bits Internal ROM 16384 8 bits SFR addressing Short direct addressing Register addressing Direct addressing Register indirect addressing Based addressing Based indexed addressing F F F F H F F 2 0 H F F 1 F H F F 0 0 H F E F F H F E E 0 H F E D F H F E 2 0 H F E 1 F H F D 0 0 H F C F F H F A E 0 H F A D F H F A C 0 H F A B F H F A 8 0 H F A 7 F...

Page 117: ...RAM 32 8 bits Use Prohibited External Memory 39552 8 bits Internal ROM 24576 8 bits SFR addressing Short direct addressing Register addressing Direct addressing Register indirect addressing Based addressing Based indexed addressing F F F F H F F 2 0 H F F 1 F H F F 0 0 H F E F F H F E E 0 H F E D F H F E 2 0 H F E 1 F H F B 0 0 H F A F F H F A E 0 H F A D F H F A C 0 H F A B F H F A 8 0 H F A 7 F ...

Page 118: ...RAM 32 8 bits Use Prohibited External Memory 31360 8 bits Internal ROM 32768 8 bits SFR addressing Short direct addressing Register addressing Direct addressing Register indirect addressing Based addressing Based indexed addressing F F F F H F F 2 0 H F F 1 F H F F 0 0 H F E F F H F E E 0 H F E D F H F E 2 0 H F E 1 F H F B 0 0 H F A F F H F A E 0 H F A D F H F A C 0 H F A B F H F A 8 0 H F A 7 F ...

Page 119: ... RAM 32 8 bits Use Prohibited External Memory 31360 8 bits Internal PROM 32768 8 bits SFR addressing Short direct addressing Register addressing Direct addressing Register indirect addressing Based addressing Based indexed addressing F F F F H F F 2 0 H F F 1 F H F F 0 0 H F E F F H F E E 0 H F E D F H F E 2 0 H F E 1 F H F B 0 0 H F A F F H F A E 0 H F A D F H F A C 0 H F A B F H F A 8 0 H F A 7 ...

Page 120: ...nd and AX register for product storage DIVUW AX register for dividend and quotient storage ADJBA ADJBS A register for storage of numeric values subject to decimal adjustment ROR4 ROL4 A register for storage of digit data which undergoes digit rotation Operand format Because implied addressing can be automatically employed with an instruction no particular operand format is necessary Description ex...

Page 121: ...lowing operand format is executed When an 8 bit register is specified one of the eight registers is specified with 3 bits in the operation code Operand format Identifier Description r X A C B E D L H rp AX BC DE HL r and rp can be described with function names X A C B E D L H AX BC DE and HL as well as absolute names R0 to R7 and RP0 to RP3 Description example MOV A C when selecting C register as ...

Page 122: ...mmediate data in an instruction word is directly addressed Operand format Identifier Description addr16 Label or 16 bit immediate data Description example MOV A 0FE00H when setting addr16 to FE00H Instruction code 1 0 0 0 1 1 1 0 OP code 0 0 0 0 0 0 0 0 00H 1 1 1 1 1 1 1 0 FEH 7 0 OP code addr16 higher Memory addr16 lower ...

Page 123: ...to FF1FH where short direct addressing is applied is a part of all SFR areas In this area ports which are frequently accessed in a program and a compare register of the timer event counter and a capture register of the timer event counter are mapped and these SFRs can be manipulated with a small number of bytes and clocks When 8 bit immediate data is at 20H to FFH bit 8 of an effective address is ...

Page 124: ... immediate data to 50H Instruction code 0 0 0 1 0 0 0 1 OP code 0 0 1 1 0 0 0 0 30H saddr offset 0 1 0 1 0 0 0 0 50H immediate data Illustration 7 0 Effective address 15 0 8 OP code saddr offset 1 1 1 1 1 1 1 α Short Direct Memory When 8 bit immediate data is 20H to FFH α 0 When 8 bit immediate data is 00H to 1FH α 1 ...

Page 125: ...FCFH and FFE0H to FFFFH However the SFR mapped at FF00H to FF1FH can also be accessed with short direct addressing Operand format Identifier Description sfr Special function register name sfrp 16 bit manipulatable special function register name even address only Description example MOV PM0 A when selecting PM0 FF20H as sfr Instruction code 1 1 1 1 0 1 1 0 OP code 0 0 1 0 0 0 0 0 20H sfr offset Ill...

Page 126: ...egister bank select flag RBS0 and RBS1 and the register pair specify code in the instruction code This addressing can be carried out for all the memory spaces Operand format Identifier Description DE HL Description example MOV A DE when selecting DE as register pair Instruction code 1 0 0 0 0 1 0 1 Illustration DE 15 0 8 D 7 7 0 E Memory Memory address specified by register pair DE The contents of...

Page 127: ...ister pair to be accessed is in the register bank specified with the register bank select flags RBS0 and RBS1 The offset data as a positive number is expanded to 16 bits to be added A carry from the 16th bit is ignored This addressing can be carried out for all the memory spaces Operand format Identifier Description HL byte Description example MOV A HL 10H When setting byte to 10H Instruction code...

Page 128: ...o be added A carry from the 16th bit is ignored This addressing can be carried out for all the memory spaces Operand format Identifier Description HL B HL C Description example In the case of MOV A HL B Instruction code 1 0 1 0 1 0 1 1 5 4 10 Stack addressing Function The stack area is indirectly addressed with the stack pointer SP contents This addressing method is automatically employed when the...

Page 129: ...put output ports Figure 6 1 shows the port types Every port is capable of 1 bit and 8 bit manipulations and can carry out considerably varied control operations Besides port functions the ports can also serve as on chip hardware input output pins Figure 6 1 Port Types Port 3 Port 5 Port 6 P00 P30 Port 0 Port 1 Port 2 Port 4 P37 P40 to P47 P50 P57 P60 P67 P04 P10 P17 P20 P27 8 ...

Page 130: ...utput specifiable bit wise SCK1 P23 If used as an input port on chip pull up resistor is enabled by software STB P24 BUSY P25 SI0 SB0 P26 SO0 SB1 P27 SCK0 P30 Port 3 TO0 P31 8 bit input output port TO1 P32 Input output specifiable bit wise TO2 P33 If used as an input port on chip pull up resistor is enabled by software TI1 P34 TI2 P35 PCL P36 BUZ P37 P40 to P47 Port 4 AD0 to AD7 8 bit input output...

Page 131: ...n P60 Port 6 N ch open drain input output port On chip P61 8 bit input output port pull up resistor can be specified by mask P62 Input output specifiable bit wise option only for mask ROM versions P63 LED can be driven directly P64 When used as an input port on chip pull up RD P65 resistor is enabled by software WR P66 WAIT P67 ASTB ...

Page 132: ...port on chip pull up resistor is enabled by software STB P24 BUSY P25 SI0 SB0 SDA0 P26 SO0 SB1 SDA1 P27 SCK0 SCL P30 Port 3 TO0 P31 8 bit input output port TO1 P32 Input output specifiable bit wise TO2 P33 If used as an input port on chip pull up resistor is enabled by software TI1 P34 TI2 P35 PCL P36 BUZ P37 P40 to P47 Port 4 AD0 to AD7 8 bit input output port Input output can be specified in 8 b...

Page 133: ... chip P61 8 bit input output port pull up resistor can be specified by mask P62 Input output specifiable bit wise option only for mask ROM versions P63 LED can be driven directly P64 When used as an input port on chip pull up RD P65 resistor is enabled by software WR P66 WAIT P67 ASTB Table 6 2 Port Functions µPD78014Y Subseries 2 2 ...

Page 134: ...nput mode output mode bit wise with the port mode register 0 PM0 P00 and P04 pins are input only ports When P01 to P03 pins are used as input ports a pull up resistor can be connected to them in 3 bit units with an on chip pull up resistor option register PUO Alternate functions include external interrupt request input external count clock input to the timer and crystal connection for subsystem cl...

Page 135: ...ort mode register RD Port 0 read signal WR Port 0 write signal Figure 6 4 P04 Block Diagram Figure 6 3 P01 to P03 Block Diagrams RD Port 0 read signal WRPUO RD WRPORT WRPM PUO0 Output Latch P01 to P03 PM01 to PM03 Selector VDD P ch P01 INTP1 to P03 INTP3 Internal Bus RD P04 XT1 Internal Bus ...

Page 136: ...with a pull up resistor option register PUO Alternate functions include an A D converter analog input RESET input sets port 1 to input mode Figure 6 5 shows a block diagram of port 1 Caution On chip pull up resistor cannot be used for pins used as A D converter analog input Figure 6 5 P10 to P17 Block Diagrams PUO Pull up resistor option register PM Port mode register RD Port 1 read signal WR Port...

Page 137: ...and 6 7 show a block diagram of port 2 Cautions 1 If used as alternate function pin set the input output latch according to the functions Refer to Figure 15 5 Serial Operating Mode Register 0 Format and Figure 17 3 Serial Operating Mode Register 1 Format for setting 2 When the status of pins is read in the SBI mode set PM2n of the PM2 to 1 n 5 or 6 refer to 15 4 3 SBI mode operation 10 Distinction...

Page 138: ...d P27 Block Diagrams µPD78014 Subseries PUO Pull up resistor option register PM Port mode register RD Port 2 read signal WR Port 2 write signal WRPUO RD WRPORT WRPM PUO2 Output Latch P22 P27 PM22 PM27 Selector VDD P ch P22 SCK1 P27 SCK0 Internal Bus Alternate Function ...

Page 139: ... 9 show a block diagram of port 2 Cautions 1 If used as alternate function pin set the input output latch according to the functions Refer to Figure 16 6 Serial Operating Mode Register 0 Format and Figure 17 3 Serial Operating Mode Register 1 Format for setting 2 When the status of pins is read in the SBI mode set PM2n of the PM2 to 1 n 5 or 6 refer to 16 4 3 SBI mode operation 10 Distinction meth...

Page 140: ...27 Block Diagrams µPD78014Y Subseries PUO Pull up resistor option register PM Port mode register RD Port 2 read signal WR Port 2 write signal WRPUO RD WRPORT WRPM PUO2 Output Latch P22 P27 PM22 PM27 Selector VDD P ch P22 SCK1 P27 SCK0 SCL Internal Bus Alternate Function ...

Page 141: ...units with a pull up resistor option register PUO Alternate functions include timer input output clock output and buzzer output RESET input sets port 3 to input mode Figure 6 10 shows a block diagram of port 3 Figure 6 10 P30 to P37 Block Diagrams PUO Pull up resistor option register PM Port mode register RD Port 3 read signal WR Port 3 write signal VDD P ch P30 TO0 P31 TO1 P32 TO2 P33 TI1 P34 TI2...

Page 142: ...functions include address data bus in external memory expansion mode RESET input sets port 4 to input mode Figure 6 11 shows a block diagram of port 4 Figure 6 12 shows a block diagram of the falling edge detector Figure 6 11 P40 to P47 Block Diagrams PUO Pull up resistor option register MM Memory expansion mode register RD Port 4 read signal WR Port 4 write signal Figure 6 12 Block Diagram of Fal...

Page 143: ... to them in 8 bit units with a pull up resistor option register PUO Port 5 can drive LEDs directly Alternate functions include address bus in external memory expansion mode RESET input sets port 5 to input mode Figure 6 13 shows a block diagram of port 5 Figure 6 13 P50 to P57 Block Diagrams PUO Pull up resistor option register PM Port mode register RD Port 5 read signal WR Port 5 write signal WRP...

Page 144: ... PUO6 Bit 6 of the pull up resistor option register P60 to P63 pins can drive LEDs directly The alternate function of the P60 to P63 pins is control signal output in external memory expansion mode RESET input sets port 6 to input mode Tables 6 14 and 6 15 show the block diagrams of port 6 Cautions 1 When external wait is not used in external memory expansion mode P66 can be used as an input output...

Page 145: ...up resistor option register PM Port mode register RD Port 6 read signal WR Port 6 write signal RD WRPORT WRPM Output Latch P60 to P63 PM60 to PM63 Selector VDD P60 to P63 Mask Option resistors Mask ROM versions only PD78P014 and 78P014Y have no pull up resistor Internal Bus µ P64 RD P65 WR P66 WAIT P67 ASTB WRPUO RD WRPORT WRPM PUO6 Output Latch P64 to P67 PM64 to PM67 Selector VDD P ch Internal B...

Page 146: ...with a 1 bit or 8 bit memory manipulation instruction RESET input sets PM0 to 1FH and other registers to FFH When a port pin is used as its alternate function pin set the port mode register and the output latch according to Table 6 5 Cautions 1 P00 and P04 pins are input only pins 2 Input output of P40 to P47 pins are specifiable with a memory expansion mode register MM 3 As port 0 is also used fo...

Page 147: ...1 P67 ASTB Output Note 2 P35 PCL Output 0 0 P36 BUZ Output 0 0 Notes 1 Read data will be undefined if the read instruction is executed for the port when used as alternate function pin 2 When pins P40 to P47 P50 to P57 and P64 to P67 are used as alternate function pins set the functions with a memory expansion mode register MM Cautions 1 When external wait is not used in memory expansion mode P66 p...

Page 148: ...5 PM14 PM13 PM12 PM11 PM10 FF21H FFH R W PM2 PM27 PM26 PM25 PM24 PM23 PM22 PM21 PM20 FF22H FFH R W PM3 PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30 FF23H FFH R W PM5 PM57 PM56 PM55 PM54 PM53 PM52 PM51 PM50 FF25H FFH R W PM6 PM67 PM66 PM65 PM64 PM63 PM62 PM61 PM60 FF26H FFH R W PMmn Pmn Pin Input Output Mode Select m 0 1 2 3 5 6 n 0 to 7 0 Output mode output buffer ON 1 Input mode output buffer OFF ...

Page 149: ...UO is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets this register to 00H Cautions 1 P00 and P04 pins do not incorporate a pull up resistor 2 When port 1 port 4 port 5 or P64 to P67 is used as an alternate function pin an on chip pull up resistor cannot be connected even if 1 is set in PUOm m 1 4 to 6 3 For P60 to P63 pins only mask ROM versions can contain pull up resi...

Page 150: ... 0 1 1 Memory 256 bytes AD0 to Port mode P64 RD expansion mode AD7 P65 WR 1 0 0 mode 4 Kbytes A8 to A11 Port mode P66 WAIT mode P67 ASTB 1 0 1 16 Kbytes A12 A13 Port mode mode 1 1 1 Full address A14 A15 modeNote Other than above Setting prohibited PW1 PW0 Wait Control 0 0 No wait 0 1 With wait 1 wait state insertion 1 0 Setting prohibited 1 1 Wait control with an external wait pin Note Full addres...

Page 151: ...input sets KRM to 02H Figure 6 19 Key Return Mode Register Format Symbol 7 6 5 4 3 2 1 0 Address When Reset R W KRM 0 0 0 0 0 0 KRMK KRIF FFF6H 02H R W KRIF Key Return Signal Detection Flag 0 Undetected 1 Detected falling edge detection of port 4 KRMK Standby Mode Control with Key Return Signal 0 Standby mode release enable 1 Standby mode release disable Caution When falling edge detection is used...

Page 152: ... since the output buffer is OFF the pin status does not change Once data is written to the output latch it is retained until data is written to the output latch again Caution In the case of 1 bit memory manipulation instruction although a single bit is manipulated the port is accessed as an 8 bit unit Therefore on a port with a mixture of input and output pins the output latch contents for pins sp...

Page 153: ...atch it is retained until data is written to the output latch again 2 Input mode The output latch contents are undefined but since the output buffer is OFF the pin status does not change Caution In the case of 1 bit memory manipulation instruction although a single bit is manipulated the port is accessed as an 8 bit unit Therefore on a port with a mixture of input and output pins the output latch ...

Page 154: ...T FUNCTIONS 154 6 5 Mask Options Mask ROM versions can contain a pull up resistor in P60 to P63 pins bit wise with the mask option The µPD78P014 and 78P014Y have no mask option and do not contain a pull up resistor for P60 to P63 pins ...

Page 155: ... the processor clock control register PPC 2 Subsystem clock oscillator Oscillates at a frequency of 32 768 kHz Oscillation cannot be stopped If the subsystem clock oscillator is not used the on chip feedback resistor can be set to disable by the processor clock control register PCC This enables to decrease power consumption in the STOP mode 7 2 Clock Generator Configuration The clock generator con...

Page 156: ...lator circuit Main system clock oscil lator circuit fXT fX STOP Internal bus Processor clock control register MCC FRC CLS CSS PCC2 PCC1 PCC0 3 Prescaler fX 2 fX 22 fX 23 fX 24 To INTP0 sampling clock Standby control circuit Wait control circuit Prescaler Watch timer clock output function Clock to peripheral hardware CPU clock Selector ...

Page 157: ...r PCC The PCC sets CPU clock selection the ratio of division main system clock oscillator operation stop and subsystem clock oscillator on chip feedback resistor enable disable The PCC is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets the PCC to 04H Figure 7 2 Feedback Resistor of Subsystem Clock XT1 XT2 FRC P ch Feedback resistor ...

Page 158: ...R CLS CPU Clock Status 0 Main system clock 1 Subsystem clock R W FRC Subsystem Clock Feedback Resistor Selection 0 On chip feedback resistor used 1 On chip feedback resistor not used R W MCC Main System Clock Oscillation ControlNote 2 0 Oscillation possible 1 Oscillation stopped Notes 1 Bit 5 is Read Only 2 When the CPU is operating on the subsystem clock MCC should be used to stop the main system...

Page 159: ...PU and minimum instruction execution time is as shown in Table 7 2 Table 7 2 Relationship between CPU Clock and Minimum Instruction Execution Time CPU Clock fCPU Minimum Instruction Execution Time 4 fCPU fX 0 4 µs fX 2 0 8 µs fX 22 1 6 µs fX 23 3 2 µs fX 24 6 4 µs fXT 122 µs fX 10 0 MHz fXT 32 768 kHz fX Main system clock oscillation frequency fXT Subsystem clock oscillation frequency ...

Page 160: ...lock Caution The STOP mode cannot be set while an external clock is being input This is because the X1 pin is short circuited to VSS in the STOP mode 7 4 2 Subsystem clock oscillator The subsystem clock oscillator oscillates with a crystal resonator standard 32 768 kHz connected to the XT1 and XT2 pins External clocks can be input to the subsystem clock oscillator In this case input a clock signal...

Page 161: ... the capacitor of the oscillator circuit at the same potential as VSS Do not connect the power source pattern through which a high current flows Do not extract signals from the oscillator Take special note of the fact that the subsystem clock oscillator is a circuit with low level amplification so that current consumption is maintained at low levels Figure 7 6 shows examples of resonator having ba...

Page 162: ...ignal extracted Remark When using a subsystem clock replace X1 and X2 with XT1 and XT2 respectively Further insert resistors in series on the side of XT2 Cautions 2 When XT2 and X1 are wired parallel X1 crosstalk noise may affect XT2 and cause an error To prevent that from happening it is recommended to connect the IC pin between XT2 and X1 to VSS as well as not wire XT2 and X1 in parallel IC X1 X...

Page 163: ...ion operations and watch operations connect the XT1 and XT2 pins as follows XT1 Connect to VDD or VSS XT2 Open In this state however some current may leak via the on chip feedback resistor of the subsystem clock oscillator when the main system clock stops To prevent that from happening the above on chip feedback resistor PCC can be removed with bit 6 FRC of the processor clock control register PCC...

Page 164: ...ystem clock selected two standby modes the STOP and HALT modes are available With the subsystem clock unused the current consumption in STOP mode can be further decreased by disabling the subsystem clock feedback resistor with PCC bit 6 FRC d The PCC can be used to select the subsystem clock and to operate the system with low current consumption 122 µs at 32 768 kHz operation e With the subsystem ...

Page 165: ...n execution time can be changed by bits 0 to 2 PCC0 to PCC2 of the PCC b If bit 7 MCC of the PCC is set to 1 when operated with the main system clock the main system clock oscillation does not stop When bit 4 CSS of the PCC is set to 1 and the operation is switched to subsystem clock operation CLS 1 after that the main system clock oscillation stops see Figure 7 7 Figure 7 7 Main System Clock Stop...

Page 166: ...n MCC is set with main system clock operation c Operation when CSS is set after setting MCC with main system clock operation MCC CSS CLS Main System Clock Oscillation Subsystem Clock Oscillation CPU Clock L L Oscillation does not stop MCC CSS CLS Main System Clock Oscillation Subsystem Clock Oscillation CPU Clock ...

Page 167: ...ocessor clock control register PCC set to 1 the following operations are carried out a The minimum instruction execution time remains constant 122 µs when operated at 32 768 kHz irrespective of bits 0 to 2 PCC0 to PCC2 of the PCC b Watchdog timer counting stops Caution Do not execute the STOP instruction while the subsystem clock is in operation ...

Page 168: ...ons 16 instructions 16 instructions 16 instructions fX 4fXT instructions 77 instructions 0 0 1 8 instructions 8 instructions 8 instructions 8 instructions fX 8fXT instructions 39 instructions 0 1 0 4 instructions 4 instructions 4 instructions 4 instructions fX 16fXT instructions 20 instructions 0 1 1 2 instructions 2 instructions 2 instructions 2 instructions fX 32fXT instructions 10 instructions ...

Page 169: ...gister PCC is rewritten and maximum speed operation is carried out 3 Upon detection of a decrease of the VDD voltage due to an interrupt request signal the main system clock is switched to the subsystem clock which must be in an oscillation stabilization state 4 Upon detection of VDD voltage reset due to an interrupt request signal 0 is set to PCC bit 7 MCC and oscillation of the main system clock...

Page 170: ...www DataSheet4U com CHAPTER 7 CLOCK GENERATOR 170 MEMO ...

Page 171: ...er and to output square waves with any selected frequency Two 8 bit timer event counters can be used as one 16 bit timer event counter See CHAPTER 9 8 BIT TIMER EVENT COUNTER 3 Watch timer TM3 This timer can set a flag every 0 5 sec and simultaneously generates interrupt requests at the preset time intervals See CHAPTER 10 WATCH TIMER 4 Watchdog timer WDTM WDTM can perform the watchdog timer funct...

Page 172: ...mer function 8 2 16 Bit Timer Event Counter Functions The 16 bit timer event counter TM0 has the following functions Interval timer PWM output Pulse width measurement External event counter Square wave output PWM output and pulse width measurement functions at the same time 1 Interval timer TM0 generates interrupt requests at the preset time interval Table 8 2 16 Bit Timer Event Counter Interval T...

Page 173: ... 800 ns 218 1 fX 26 2 ms 22 1 fX 400 ns 24 1 fX 1 6 µs 219 1 fX 52 4 ms 23 1 fX 800 ns Remarks 1 fX Main system clock oscillation frequency 2 Values in parentheses apply to operation with fX 10 0 MHz 8 3 16 Bit Timer Event Counter Configuration The 16 bit timer event counter consists of the following hardware Table 8 4 16 Bit Timer Event Counter Configuration Item Configuration Timer register 16 b...

Page 174: ...bit compare register CR00 Match Match fX 2 fX 22 fX 23 TI0 P00 INTP0 Selector Note 1 TCL06 TCL05 TCL04 Timer clock select register 0 16 bit capture register CR01 16 bit timer register lower 8 bits TM0L 16 bit timer register upper 8 bits TM0H 0 15 Clear Selector 3 3 2 TMC03 TMC02 TMC01 OVF0 LVS0 LVR0 TOC01 TOE0 16 bit timer event counter output control circuit OVF 0 15 7 16 bit timer mode control r...

Page 175: ...ted line is included in the output control circuit Internal bus Internal bus 16 bit compare register CR00 16 bit timer register TM0 16 bit capture register CR01 PWM pulse generator Selector 3 TCL06 TCL05 TCL04 fX 2 fX 22 fX 23 Timer clock select register 0 TOC01 TOE0 P30 output latch PM30 16 bit timer output control register Port mode register 3 TO0 P30 Selector ...

Page 176: ... Block Diagram Remark The circuitry enclosed by the dotted line is the output control circuit LVR0 LVS0 TOC01 INTTM0 TI0 P00 INTP0 PWM pulse generator Edge detector circuit 2 ES10 ES11 3 Selector R S INV Q TMC01 to TMC03 TOC01 TMC01 to TMC03 TOE0 3 Selector Active level control P30 output latch PM30 TO0 P30 Level F F LV0 ...

Page 177: ...tion is less than the value of the 16 bit timer register TM0 TM0 keeps on counting and resumes counting from 0 after an overflow When the value of CR00 posterior to alteration is less than the value prior to alteration the timer must be restarted after CR00 is altered 2 16 bit capture register CR01 CR01 is a 16 bit register capturing the content of 16 bit timer register TM0 Capture trigger is INTP...

Page 178: ...it timer output control register TOC0 Port mode register 3 PM3 External interrupt mode register INTM0 Sampling clock select register SCS 1 Timer clock select register 0 TCL0 This register is used to set the count clock of the 16 bit timer register TCL0 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets TCL0 to 00H Remark TCL0 has the function of setting the PCL output cl...

Page 179: ...d 1 Output enabled Cautions 1 Setting of the INTP0 P00 TI0 pin valid edge is performed by external interrupt mode register INTM0 and selection of the sampling clock frequency is performed by the sampling clock selection register SCS 2 When enabling PCL output set TCL00 to TCL03 then set 1 in CLOE with a 1 bit memory manipulation instruction 3 To read the count value when TI0 has been specified as ...

Page 180: ...t timer register clear mode and output timing and detects an overflow TMC0 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets TMC0 value to 00H Caution The 16 bit timer register TM0 starts operation when TMC01 to TMC03 are set to the value other than 0 0 0 operation stop mode To stop the timer operation set TMC01 through TCM03 to 0 0 0 ...

Page 181: ...ween TM0 and edge CR00 1 0 1 Match between TM0 and CR00 or TI0 valid edge 1 1 0 Clear start on match Match between TM0 and between TM0 and CR00 CR00 1 1 1 Match between TM0 and CR00 or TI0 valid edge Cautions 1 Switch the clear mode and the TO0 output timing after stopping the timer operation by setting TMC01 through TMC03 to 0 0 0 2 Set the valid edge of the INTP0 P00 TI0 pin with an external int...

Page 182: ... Bit Timer Output Control Register Format Symbol 7 6 5 4 3 2 1 0 Address When Reset R W TOC0 0 0 0 0 LVS0 LVR0 TOC01 TOE0 FF4EH 00H R W Cautions 1 Timer operation must be stopped before setting TOC0 2 If LVS0 and LVR0 are read after data is set they will be 0 TOE0 16 Bit Timer Event Counter Output Control 0 Output disabled Port mode 1 Output enabled TOC01 In PWM Mode In Other Modes Active level Ti...

Page 183: ...M30 and output latch of P30 to 0 PM3 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PM3 value to FFH Figure 8 7 Port Mode Register 3 Format Symbol 7 6 5 4 3 2 1 0 Address When Reset R W PM3 PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30 FF23H FFH R W PM3n P3n Pin Input Output Mode Selection n 0 to 7 0 Output mode output buffer ON 1 Input mode output buffer OFF ...

Page 184: ...hen Reset R W INTM0 ES31 ES30 ES21 ES20 ES11 ES10 0 0 FFECH 00H R W ES11 ES10 INTP0 Valid Edge Selection 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both falling and rising edge ES21 ES20 INTP1 Valid Edge Selection 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both falling and rising edge ES31 ES30 INTP2 Valid Edge Selection 0 0 Falling edge 0 1 Rising edge 1 0 Settin...

Page 185: ... 9 Sampling Clock Select Register Format Caution fX 2N 1 is the clock supplied to the CPU and fX 26 and fX 27 are clocks supplied to peripheral hardware fX 2N 1 is stopped in HALT mode Remarks 1 N Value set in bit 0 to bit 2 PCC0 to PCC2 of the processor clock control register PCC N 0 to 4 2 fX Main system clock oscillation frequency 3 Values in parentheses apply to operation with fX 10 0 MHz Symb...

Page 186: ...alue of the 16 bit timer register TM0 matches the value set to CR00 counting continues with the TM0 value cleared to 0 and the interrupt request signal INTTM0 is generated Count clock of the 16 bit timer event counter can be selected with bits 4 to 6 TCL04 to TCL06 of the timer clock select register 0 TCL0 For the operation after changing compare register value during timer count operation refer t...

Page 187: ... fX 13 1 ms 2 1 fX 200 ns 0 1 1 23 1 fX 800 ns 218 1 fX 26 2 ms 22 1 fX 400 ns 1 0 0 24 1 fX 1 6 µs 219 1 fX 52 4 ms 23 1 fX 800 ns Other than above Setting prohibited Remarks 1 fX Main system clock oscillation frequency 2 TCL04 to TCL06 Bits 4 to 6 of the timer clock select register 0 TCL0 3 Values in parentheses apply to operation with fX 10 0 MHz Count clock TM0 Count value Count start Clear Cl...

Page 188: ...register TOC0 This PWM pulse has a 14 bit resolution The pulse can be converted to an analog voltage by integrating it with an external low pass filter LPF The PWM pulse has a combination of the basic cycle determined by 28 fΦ and the sub cycle determined by 214 fΦ so that the time constant of the external LPF can be shortened Count clock fΦ can be selected with bits 4 to 6 TCL04 to TCL06 of the t...

Page 189: ...are register CR00 value VAN VREF 216 VREF External switching circuit reference voltage Figure 8 12 Example of D A Converter Configuration with PWM Output Figure 8 13 shows an example in which PWM output is converted to an analog voltage and used in a voltage synthesizer type TV tuner Figure 8 13 TV Tuner Application Circuit Example TO0 P30 Switching circuit PWM signal VREF Low pass filter Analog o...

Page 190: ...e register INTM0 is input the value of TM0 is taken into 16 bit capture register CR01 and an external interrupt request signal INTP0 is set Any of three edge specifications can be selected rising falling or both edges by means of bits 2 and 3 ES10 and ES11 of the external interrupt mode register INTM0 For valid edge detection sampling is performed at the interval selected by means of the sampling ...

Page 191: ...TER Figure 8 15 Timing of Pulse Width Measurement Operation by Free Running Counter with Both Edges Specified Count Clock TM0 Count Value 0000 0001 D0 D1 FFFF 0000 D2 D3 TI0 Pin Input CR01 Captured Value D0 D1 D2 D3 INTP0 OVF0 D1 D0 t 10000H D1 D2 t D3 D2 t t ...

Page 192: ...n can be selected from three types rising falling and both edges by bit 2 and bit 3 ES10 and ES11 of the external interrupt mode register INTM0 In a valid edge detection the sampling is performed by a cycle selected by the sampling clock select register SCS and a capture operation is not performed before detecting valid levels twice allowing short pulse width noise to be eliminated Figure 8 16 Tim...

Page 193: ...e interrupt request signal INTTM0 is generated The 16 bit compare register CR00 must be set to a value other than 0000H 1 pulse count operation is prohibited The rising edge the falling edge or both edges can be selected with bits 2 and 3 ES10 and ES11 of INTM0 Because operation is carried out only after the valid edge is detected twice by sampling at the cycle selected with the sampling clock sel...

Page 194: ... 194 CHAPTER 8 16 BIT TIMER EVENT COUNTER Figure 8 18 External Event Counter Operation Timings with Rising Edge Specified TI0 Pin Input TM0 Count Value 0000 0001 0002 0003 0004 0005 N 1 N 0000 0001 0002 0003 CR00 N INTTM0 ...

Page 195: ... Output Ranges TCL06 TCL05 TCL04 Minimum Pulse Width Maximum Pulse Width Resolution 0 0 0 2 TI0 input cycle 216 TI0 input cycle TI0 input edge cycle 0 1 0 22 1 fX 400 ns 217 1 fX 13 1 ms 2 1 fX 200 ns 0 1 1 23 1 fX 800 ns 218 1 fX 26 2 ms 22 1 fX 400 ns 1 0 0 24 1 fX 1 6 µs 219 1 fX 52 4 ms 23 1 fX 800 ns Remarks 1 fX Main system clock oscillation frequency 2 TCL04 to TCL06 Bit 4 to bit 6 of timer...

Page 196: ...ng the 16 bit compare register as event counter one pulse count operation cannot be carried out 3 Operation after compare register change during timer count operation If the value after the 16 bit compare register CR00 is changed is smaller than that of the 16 bit timer register TM0 TM0 continues counting and then restarts counting from 0 Therefore if the value after CR00 changes M is smaller than...

Page 197: ...Figure 8 22 Capture Register Data Retention Timings 5 Valid edge set Set the valid edge of the TI0 INTP0 P00 pin after setting bits 1 to 3 TMC01 to TMC03 of the 16 bit timer mode control register TMC0 to 0 0 and 0 respectively and then stopping timer operation Valid edge setting is carried out with bits 2 and 3 ES10 and ES11 of the external interrupt mode register INTM0 Count Pulse TM0 Count Value...

Page 198: ...VF0 flag operation OVF0 flag is set to 1 When clear start mode on match between TM0 and CR00 is selected CR00 is set to FFFFH TM0 is counted up from FFFFH to 0000H Figure 8 23 OVF0 Flag Operation Timing Count Pulse CR00 TM0 OVF0 INTTM00 FFFFH FFFEH FFFFH 0000H 0001H ...

Page 199: ...he following two modes are available 8 bit timer event counter mode two channel 8 bit timer event counters to be used separately 16 bit timer event counter mode two channel 8 bit timer event counters to be used together as 16 bit timer event counter 9 1 1 8 bit timer event counter mode The 8 bit timer event counters 1 and 2 TM1 and TM2 have the following functions Interval timer External event cou...

Page 200: ...8 µs 23 1 fX 800 ns 24 1 fX 1 6 µs 212 1 fX 409 6 µs 24 1 fX 1 6 µs 25 1 fX 3 2 µs 213 1 fX 819 2 µs 25 1 fX 3 2 µs 26 1 fX 6 4 µs 214 1 fX 1 64 ms 26 1 fX 6 4 µs 27 1 fX 12 8 µs 215 1 fX 3 28 ms 27 1 fX 12 8 µs 28 1 fX 25 6 µs 216 1 fX 6 55 ms 28 1 fX 25 6 µs 29 1 fX 51 2 µs 217 1 fX 13 1 ms 29 1 fX 51 2 µs 210 1 fX 102 4 µs 218 1 fX 26 2 ms 210 1 fX 102 4 µs 212 1 fX 409 6 µs 220 1 fX 104 9 ms 2...

Page 201: ...X 3 28 ms 27 1 fX 12 8 µs 28 1 fX 25 6 µs 216 1 fX 6 55 ms 28 1 fX 25 6 µs 29 1 fX 51 2 µs 217 1 fX 13 1 ms 29 1 fX 51 2 µs 210 1 fX 102 4 µs 218 1 fX 26 2 ms 210 1 fX 102 4 µs 212 1 fX 409 6 µs 220 1 fX 104 9 ms 212 1 fX 409 6 µs Remarks 1 fX Main system clock oscillation frequency 2 Values in parentheses apply to operation with fX 10 0 MHz 2 External event counter The number of pulses of an exte...

Page 202: ...ms 22 1 fX 400 ns 23 1 fX 800 ns 219 1 fX 52 4 ms 23 1 fX 800 ns 24 1 fX 1 6 µs 220 1 fX 104 9 ms 24 1 fX 1 6 µs 25 1 fX 3 2 µs 221 1 fX 209 7 ms 25 1 fX 3 2 µs 26 1 fX 6 4 µs 222 1 fX 419 4 ms 26 1 fX 6 4 µs 27 1 fX 12 8 µs 223 1 fX 838 9 ms 27 1 fX 12 8 µs 28 1 fX 25 6 µs 224 1 fX 1 7 s 28 1 fX 25 6 µs 29 1 fX 51 2 µs 225 1 fX 3 7 s 29 1 fX 51 2 µs 210 1 fX 102 4 µs 226 1 fX 6 7 s 210 1 fX 102 4...

Page 203: ... fX 400 ns 218 1 fX 26 2 ms 22 1 fX 400 ns 23 1 fX 800 ns 219 1 fX 52 4 ms 23 1 fX 800 ns 24 1 fX 1 6 µs 220 1 fX 104 9 ms 24 1 fX 1 6 µs 25 1 fX 3 2 µs 221 1 fX 209 7 ms 25 1 fX 3 2 µs 26 1 fX 6 4 µs 222 1 fX 419 4 ms 26 1 fX 6 4 µs 27 1 fX 12 8 µs 223 1 fX 838 9 ms 27 1 fX 12 8 µs 28 1 fX 25 6 µs 224 1 fX 1 7 s 28 1 fX 25 6 µs 29 1 fX 51 2 µs 225 1 fX 3 4 s 29 1 fX 51 2 µs 210 1 fX 102 4 µs 226 ...

Page 204: ...9 5 8 Bit Timer Event Counter Configuration Item Configuration Timer register 8 bits 2 TM1 TM2 Register 8 bit compare register 2 CR10 CR20 Timer output 2 TO1 TO2 Control registers Timer clock select register 1 TCL1 8 bit timer mode control register TMC1 8 bit timer output control register TOC1 Port mode register 3 PM3 Note Note Refer to Figure 6 10 P30 to P37 Block Diagrams ...

Page 205: ...r 1 TM1 Clear 4 TCL 17 TCL 16 TCL 15 TCL 14 TCL 13 TCL 12 TCL 11 TCL 10 Timer Clock Select Register 1 TMC12 TCE2 TCE1 8 Bit Timer Mode Control Register 8 Bit Timer Register 1 TM2 Clear Note Note 8 Bit Timer Event Counter Output Control Circuit 1 4 LVS2 LVR2 TOC 15 TOE2 LVS1 LVR1 TOC 11 TOE1 8 Bit Timer Output Control Register INTTM1 8 Bit Timer Event Counter Output Control Circuit 2 4 TO2 P32 INTT...

Page 206: ...an output control circuit Figure 9 3 8 Bit Timer Event Counter Output Control Circuit 2 Block Diagram Note Bit 2 of the port mode register 3 PM3 Remarks 1 The section in the broken line is an output control circuit 2 fSCK Serial clock frequency LVR1 LVS1 INTTM1 R S INV TOE1 P31 Output Latch PM31Note TOC11 TO1 P31 Q Level F F LV1 LVR2 LVS2 INTTM2 R fSCK S INV TOE2 P32 Output Latch PM32Note TOC15 TO...

Page 207: ...of CR10 and CR20 posterior to alteration are less than the values of the 8 bit timer registers TM1 and TM2 TM1 and TM2 keep on counting and resume counting from 0 after an overflow When the values of CR10 and CR20 posterior to alteration are less than the values prior to alteration the timer must be restarted after CR10 and CR20 are altered 2 8 bit timer registers 1 2 TM1 TM2 These are 8 bit regis...

Page 208: ...z 1 1 1 1 fX 212 2 4 kHz Other than above Setting prohibited TCL17 TCL16 TCL15 TCL14 8 bit Timer Register 2 Clock Selection 0 0 0 0 TI2 falling edge 0 0 0 1 TI2 rising edge 0 1 1 0 fX 22 2 5 MHz 0 1 1 1 fX 23 1 25 MHz 1 0 0 0 fX 24 625 kHz 1 0 0 1 fX 25 313 kHz 1 0 1 0 fX 26 156 kHz 1 0 1 1 fX 27 78 1 kHz 1 1 0 0 fX 28 39 1 kHz 1 1 0 1 fX 29 19 5 kHz 1 1 1 0 fX 210 9 8 kHz 1 1 1 1 fX 212 2 4 kHz O...

Page 209: ...ter Format Cautions 1 Switch the operating mode after stopping timer operation 2 When used as 16 bit timer register TMS TCE1 should be used for operation enable stop Symbol 7 6 5 4 3 2 1 0 Address When Reset R W TMC1 0 0 0 0 0 TMC12 TCE2 TCE1 FF49H 00H R W TCE1 8 Bit Timer Register 1 Operation Control 0 Operation stop TM1 clear to 0 1 Operation enable TCE2 8 Bit Timer Register 2 Operation Control ...

Page 210: ...Control 0 Output disable port mode 1 Output enable TOC11 8 Bit Timer Event Counter 1 Timer Output F F Control 0 Inverted operation disable 1 Inverted operation enable LVS1 LVR1 8 Bit Timer Event Counter 1 Timer Output F F Status Set 0 0 Unchanged 0 1 Timer output F F reset 0 1 0 Timer output F F reset 1 1 1 Setting prohibited TOE2 8 Bit Timer Event Counter 2 Output Control 0 Output disable port mo...

Page 211: ...set output latches PM31 PM32 and P31 P32 to 0 PM3 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PM3 to FFH Figure 9 7 Port Mode Register 3 Format Symbol 7 6 5 4 3 2 1 0 Address When Reset R W PM3 PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30 FF23H FFH R W PM3n P3n Pin Input Output Mode Selection n 0 to 7 0 Output mode output buffer ON 1 Input mode output buffer OFF ...

Page 212: ...ed to 0 and the interrupt request signals INTTM1 and INTTM2 are generated Count clock of TM1 can be selected with bits 0 to 3 TCL10 toTCL13 of the timer clock select register 1 TCL1 Count clock of TM2 can be selected with bits 4 to 7 TCL14 toTCL17 of the timer clock select register 1 TCL1 For the operation after changing compare register value during timer count operation refer to 9 5 Cautions on ...

Page 213: ... Interval Time Resolution 0 0 0 0 TI2 input cycle 28 TI2 input cycle TI2 input edge cycle 0 0 0 1 TI2 input cycle 28 TI2 input cycle TI2 input edge cycle 0 1 1 0 22 1 fX 400 ns 210 1 fX 102 4 µs 22 1 fX 400 ns 0 1 1 1 23 1 fX 800 ns 211 1 fX 204 8 µs 23 1 fX 800 ns 1 0 0 0 24 1 fX 1 6 µs 212 1 fX 409 6 µs 24 1 fX 1 6 µs 1 0 0 1 25 1 fX 3 2 µs 213 1 fX 819 2 µs 25 1 fX 3 2 µs 1 0 1 0 26 1 fX 6 4 µs...

Page 214: ...the valid edge specified with the timer clock select register 1 TCL1 is input Either the rising or falling edge can be selected When the TM1 and TM2 counted values match the values of 8 bit compare registers CR10 and CR20 TM1 and TM2 are cleared to 0 and the interrupt request signals INTTM1 and INTTM2 are generated Figure 9 9 External Event Counter Operation Timings with Rising Edge Specified Rema...

Page 215: ...ply to operation with fX 10 0 MHz Figure 9 10 Square Wave Output Operation Timings TCL13 TCL12 TCL11 TCL10 Minimum Pulse Width Maximum Pulse Width Resolution 0 1 1 0 22 1 fX 400 ns 210 1 fX 102 4 µs 22 1 fX 400 ns 0 1 1 1 23 1 fX 800 ns 211 1 fX 204 8 µs 23 1 fX 800 ns 1 0 0 0 24 1 fX 1 6 µs 212 1 fX 409 6 µs 24 1 fX 1 6 µs 1 0 0 1 25 1 fX 3 2 µs 213 1 fX 819 2 µs 25 1 fX 3 2 µs 1 0 1 0 26 1 fX 6 ...

Page 216: ...e count value the upper 8 bit value is set as CR20 and the lower 8 bit value as CR10 For the count value interval time which can be set refer to Table 9 9 When the 8 bit timer register 1 TM1 and CR10 values match and the 8 bit timer register 2 TM2 and CR20 values match counting continues with the TM1 and TM2 values cleared to 0 and the interrupt request signal INTTM2 is generated For the operation...

Page 217: ...0 0 0 TI1 input cycle 28 TI1 input cycle TI1 input edge cycle 0 0 0 1 TI1 input cycle 28 TI1 input cycle TI1 input edge cycle 0 1 1 0 22 1 fX 400 ns 218 1 fX 26 2 ms 22 1 fX 400 ns 0 1 1 1 23 1 fX 800 ns 219 1 fX 52 4 ms 23 1 fX 800 ns 1 0 0 0 24 1 fX 1 6 µs 220 1 fX 104 9 ms 24 1 fX 1 6 µs 1 0 0 1 25 1 fX 3 2 µs 221 1 fX 209 7 ms 25 1 fX 3 2 µs 1 0 1 0 26 1 fX 6 4 µs 222 1 fX 419 4 ms 26 1 fX 6 4...

Page 218: ...bit compare registers CR10 and CR20 TM1 and TM2 are cleared to 0 and the interrupt request signal INTTM2 is generated Figure 9 12 External Event Counter Operation Timings with Rising Edge Specified Caution Even if the 16 bit timer event counter mode is used when the TM1 count value matches the CR10 value interrupt request INTTM1 is generated and the F F of 8 bit timer event counter output control ...

Page 219: ...Pulse Width Resolution 0 1 1 0 22 1 fX 400 ns 218 1 fX 26 2 ms 22 1 fX 400 ns 0 1 1 1 23 1 fX 800 ns 219 1 fX 52 4 ms 23 1 fX 800 ns 1 0 0 0 24 1 fX 1 6 µs 220 1 fX 104 9 ms 24 1 fX 1 6 µs 1 0 0 1 25 1 fX 3 2 µs 221 1 fX 209 7 ms 25 1 fX 3 2 µs 1 0 1 0 26 1 fX 6 4 µs 222 1 fX 419 4 ms 26 1 fX 6 4 µs 1 0 1 1 27 1 fX 12 8 µs 223 1 fX 838 9 ms 27 1 fX 12 8 µs 1 1 0 0 28 1 fX 25 6 µs 224 1 fX 1 7 s 28...

Page 220: ...ompare registers 1 and 2 sets The 8 bit compare registers CR10 and CR20 can be set to 00H Therefore when the 8 bit compare register is used as event counter one pulse count operation can be carried out When the 8 bit compare registers are used as 16 bit timer event counter write data to CR10 and CR20 after setting bit 0 TCE1 of the 8 bit timer mode control register TMC1 to 0 and stopping timer ope...

Page 221: ...those of 8 bit timer registers TM1 and TM2 TM1 and TM2 continue counting overflow and then restart counting from 0 Thus if the value after CR10 and CR20 M change is smaller than that before change N it is necessary to restart the timer after changing CR10 and CR20 Figure 9 16 Timings after Compare Register Change during Timer Count Operation Remark N X M Count Pulse CR10 CR20 N M TM1 TM2 Count Val...

Page 222: ...www DataSheet4U com CHAPTER 9 8 BIT TIMER EVENT COUNTER 222 MEMO ...

Page 223: ...y other than above is used a flag WTIF is not set at 0 5 0 25 or 0 5 1 0 intervals Caution When 8 38 MHz or 4 19 MHz frequency is used a time interval has a little error 2 Interval timer Interrupt requests INTTM3 are generated at the preset time interval Table 10 1 Interval Timer Interval Time Interval Time When operated When operated at When operated at When operated at at fX 10 0 MHz fX 8 38 MHz...

Page 224: ... 10 3 Watch Timer Control Registers The following two types of registers are used to control the watch timer Timer clock select register 2 TCL2 Watch timer mode control register TMC2 1 Timer clock select register 2 TCL2 Refer to Figure 10 2 This register sets the watch timer count clock TCL2 is set with an 8 bit memory manipulation instruction RESET input sets TCL2 to 00H Remark Besides setting th...

Page 225: ...am fX 28 fXT fW TMC21 Clear Prescaler TCL24 Timer Clock Select Register 2 5 Bit Counter Clear INTWT INTTM3 3 TMC26 TMC25 TMC24 TMC23 TMC22 TMC21 TMC20 Watch Timer Mode Control Register Internal Bus Selector fW 24 fW 25 fW 26 fW 27 fW 28 fW 29 fW 213 fW 214 Selector Selector Selector ...

Page 226: ...Hz 1 1 0 fX 210 9 8 kHz 1 1 1 fX 212 2 4 kHz TCL24 Watch Timer Count Clock Selection 0 fX 28 39 1 kHz 1 fXT 32 768 kHz TCL27 TCL26 TCL25 Buzzer Output Frequency Selection 0 Buzzer output disable 1 0 0 fX 210 9 8 kHz 1 0 1 fX 211 4 9 kHz 1 1 0 fX 212 2 4 kHz 1 1 1 Setting prohibited Caution If data other than identical data is to be rewritten to TCL2 the timer operation must be stopped first Remark...

Page 227: ...n 0 0 0 24 fW 488 µs 0 0 1 25 fW 977 µs 0 1 0 26 fW 1 95 ms 0 1 1 27 fW 3 91 ms 1 0 0 28 fW 7 81 ms 1 0 1 29 fW 15 6 ms Other than above Setting prohibited Note Do not frequently clear the prescaler when using the watch timer Remarks 1 fW Watch timer clock frequency fX 28 or fXT 2 Values in parentheses apply to operation with fW 32 768 kHz 2 Watch timer mode control register TMC2 This register set...

Page 228: ...0 5005136 second fX 8 38 106 When fX 4 19 MHz frequency is used 28 213 221 0 5005136 second fX 4 19 106 When fXT 32 768 MHz frequency is used 1 214 214 0 50000 second fXT 32 768 103 When fX 10 0 MHz frequency is used not intended 28 214 222 0 4194304 second fX 10 0 106 The watch timer sets the interrupt request flag WTIF to 1 at the constant time interval The standby state STOP mode HALT mode can ...

Page 229: ...erated at When operated at When operated at at fX 10 0 MHz fX 8 38 MHz fX 4 19 MHz fXT 32 768 kHz 0 0 0 24 1 fW 409 6 µs 489 µs 978 µs 488 µs 0 0 1 25 1 fW 819 2 µs 978 µs 1 96 ms 977 µs 0 1 0 26 1 fW 1 64 ms 1 96 ms 3 91 ms 1 95 ms 0 1 1 27 1 fW 3 28 ms 3 91 ms 7 82 ms 3 91 ms 1 0 0 28 1 fW 6 55 ms 7 82 ms 15 6 ms 7 81 ms 1 0 1 29 1 fW 13 1 ms 15 6 ms 31 3 ms 15 6 ms Other than above Setting proh...

Page 230: ...www DataSheet4U com CHAPTER 10 WATCH TIMER 230 MEMO ...

Page 231: ...imer Inadvertent Program Loop Detection Time Inadvertent Program Loop When operated at Inadvertent Program Loop When operated at Detection Time fX 10 0 MHz Detection Time fX 10 0 MHz 212 1 fX 409 6 µs 216 1 fX 6 55 µs 213 1 fX 819 2 µs 217 1 fX 13 1 µs 214 1 fX 1 64 ms 218 1 fX 26 2 ms 215 1 fX 3 28 ms 220 1 fX 104 9 ms Remark fX Main system clock oscillation frequency 2 Interval timer mode Interr...

Page 232: ...TIMER 232 11 2 Watchdog Timer Configuration The watchdog timer consists of the following hardware Table 11 3 Watchdog Timer Configuration Item Configuration Control register Timer clock select register 2 TCL2 Watchdog timer mode register WDTM ...

Page 233: ...rnal Bus Internal Bus fX 24 8 Bit Prescaler fX 25 fX 26 fX 27 fX 28 fX 29 fX 210 fX 212 Selector 3 8 Bit Counter RUN Clear TMIF4 TMMK4 TCL22 RUN TCL21 TCL20 Timer Clock Select Register 2 Watchdog Timer Mode Register INTWDT Maskable Interrupt Request RESET INTWDT Non Maskable Interrupt Request Control Circuit ...

Page 234: ...r Timer clock select register 2 TCL2 Watchdog timer mode register WDTM 1 Timer clock select register 2 TCL2 This register sets the watchdog timer count clock TCL2 is set with an 8 bit memory manipulation instruction RESET input sets TCL2 to 00H Remark Besides setting the watchdog timer count clock TCL2 sets the watch timer count clock and buzzer output frequency ...

Page 235: ... kHz 1 1 0 fX 210 9 8 kHz 1 1 1 fX 212 2 4 kHz TCL24 Watch Timer Count Clock Selection 0 fX 28 39 1 kHz 1 fXT 32 768 kHz TCL27 TCL26 TCL25 Buzzer Output Frequency Selection 0 Buzzer output disable 1 0 0 fX 210 9 8 kHz 1 0 1 fX 211 4 9 kHz 1 1 0 fX 212 2 4 kHz 1 1 1 Setting prohibited Caution If data other than identical data is to be rewritten to TCL2 the timer operation must be stopped first Rema...

Page 236: ...g timer mode 2 Reset operation is activated upon generation of an overflow RUN Watchdog Timer Operation SelectionNote 3 0 Count stop 1 Counter is cleared and counting starts Notes 1 Once set to 1 WDTM3 and WDTM4 cannot be cleared to 0 by software 2 Interval timer operation starts when the RUN bit is set to 1 3 Once set to 1 RUN cannot be cleared to 0 by software Thus once counting starts it can on...

Page 237: ...kable interrupt request is generated according to the WDTM bit 3 WDTM3 value Watchdog timer can be cleared by setting RUN to 1 The watchdog timer continues operating in the HALT mode but it stops in the STOP mode Thus set RUN to 1 before the STOP mode is set clear the watchdog timer and then execute the STOP instruction Cautions 1 The actual inadvertent program loop detection time may be shorter t...

Page 238: ...ity The interval timer continues operating in the HALT mode but it stops in the STOP mode Thus set WDTM bit 7 RUN to 1 before the STOP mode is set clear the interval timer and then execute the STOP instruction Cautions 1 Once bit 4 WDTM4 of WDTM is set to 1 with the watchdog timer mode selected the interval timer mode is not set unless RESET input is applied 2 The interval time just after setting ...

Page 239: ...ow the procedure below to output clock pulses 1 Select the clock pulse output frequency with clock pulse output disabled with bits 0 to 3 TCL00 to TCL03 of TCL0 2 Set the P35 output latch to 0 3 Set bit 5 PM35 of port mode register 3 PM3 to 0 set to output mode 4 Set bit 7 CLOE of TCL0 to 1 Caution Clock output cannot be used if P35 output latch is set to 1 Remark When clock output enable disable ...

Page 240: ...Control Registers The following two types of registers are used to control the clock output function Timer clock select register 0 TCL0 Port mode register 3 PM3 1 Timer clock select register 0 TCL0 This register sets PCL output clock TCL0 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets TCL0 to 00H Remark Besides setting PCL output clock TCL0 sets the 16 bit timer regi...

Page 241: ...must be stopped first Remarks 1 fX Main system clock oscillation frequency 2 fXT Subsystem clock oscillation frequency 3 TI0 16 bit timer event counter input pin 4 TM0 16 bit timer register 5 Values in parentheses apply to operation with fX 10 0 MHz or fXT 32 768 kHz Symbol 7 6 5 4 3 2 1 0 Address When Reset R W TCL CLOE TCL06 TCL05 TCL04 TCL03 TCL02 TCL01 TCL00 FF40H 00H R W TCL03 TCL02 TCL01 TCL...

Page 242: ...tion set PM35 and output latch of P35 to 0 PM3 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PM3 to FFH Figure 12 4 Port Mode Register 3 Format Symbol 7 6 5 4 3 2 1 0 Address When Reset R W PM3 PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30 FF23H 00H R W PM3n P3n Pin Input Output Mode Selection n 0 to 7 0 Output mode output buffer ON 1 Input mode output buffer OFF ...

Page 243: ...5 to 7 TCL25 to TCL27 of TCL2 2 Set the P36 output latch to 0 3 Set bit 6 PM36 of port mode register 3 PM3 to 0 Set to output mode Caution Buzzer output cannot be used if P36 output latch is set to 1 13 2 Buzzer Output Control Circuit Configuration The buzzer output control circuit consists of the following hardware Table 13 1 Buzzer Output Control Circuit Configuration Item Configuration Control ...

Page 244: ...zzer output function Timer clock select register 2 TCL2 Port mode register 3 PM3 1 Timer clock select register 2 TCL2 This register sets the buzzer output frequency TCL2 is set with an 8 bit memory manipulation instruction RESET input sets TCL2 to 00H Remark Besides setting the buzzer output frequency TCL2 sets the watch timer count clock and the watchdog timer count clock ...

Page 245: ...0 MHz or fXT 32 768 kHz Symbol 7 6 5 4 3 2 1 0 Address When Reset R W TCL2 TCL27 TCL26 TCL25 TCL24 0 TCL22 TCL21 TCL20 FF42H 00H R W TCL22 TCL21 TCL20 Watchdog Timer Count Clock Selection 0 0 0 fX 24 625 kHz 0 0 1 fX 25 313 kHz 0 1 0 fX 26 156 kHz 0 1 1 fX 27 78 1 kHz 1 0 0 fX 28 39 1 kHz 1 0 1 fX 29 19 5 kHz 1 1 0 fX 210 9 8 kHz 1 1 1 fX 212 2 4 kHz TCL24 Watch Timer Count Clock Selection 0 fX 28...

Page 246: ...tion set PM36 and output latch of P36 to 0 PM3 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PM3 to FFH Figure 13 3 Port Mode Register 3 Format Symbol 7 6 5 4 3 2 1 0 Address When Reset R W PM3 PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30 FF23H 00H R W PM3n P3n Pin Input Output Mode Selection n 0 to 7 0 Output mode output buffer ON 1 Input mode output buffer OFF ...

Page 247: ...D converter mode register ADM One channel of analog input is selected from ANI0 to ANI7 and A D conversion is carried out In the case of hardware start A D conversion operation stops when it terminates and an interrupt request INTAD is generated In the case of software start the A D conversion operation is repeated Each time an A D conversion operation ends an interrupt request INTAD is generated ...

Page 248: ...er ADIS3 ADIS2 ADIS1 ADIS0 4 ANI0 P10 ANI1 P11 ANI2 P12 ANI3 P13 ANI4 P14 ANI5 P15 ANI6 P16 ANI7 P17 3 ADM1 to ADM3 Sample and Hold Circuit Voltage Comparator Series Resistor String AVREF AVSS Successive Approxi mation Register INTP3 P03 Trigger Enable Falling Edge Detection Circuit Control Circuit 3 INTAD INTP3 CS TRG FR1 FR0 ADM3 ADM2 ADM1 A D Conversion Result Register ADCR A D Converter Mode R...

Page 249: ...es resistor string is connected to among AVREF to AVSS and generates a voltage to be compared to the analog input 6 ANI0 to ANI7 pins These are 8 channel analog input pins to input analog signals to undergo A D conversion to the A D converter These pins except analog input pins selected with the A D converter input select register ADIS can be used as the input output port Cautions 1 Use ANI0 to AN...

Page 250: ...ies resistor string of approximately 10 kΩ is connected between the AVREF pin and the AVSS pin Therefore if the output impedance of the reference voltage source is high this will result in parallel connection to the series resistor string between the AVREF pin and the AVSS pin and there will be a large reference voltage error 8 AVSS pin Ground potential pin of the A D converter It must be at the s...

Page 251: ...ol the A D converter A D converter mode register ADM A D converter input select register ADIS 1 A D converter mode register ADM This register sets the analog input channel for A D conversion conversion time conversion start stop and external trigger ADM is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets ADM to 01H ...

Page 252: ...ion Remark fX Main system clock oscillation frequency Symbol 7 6 5 4 3 2 1 0 Address When Reset R W ADM CS TRG FR1 FR0 ADM3 ADM2 ADM1 1 FF80H 01H R W ADM3 ADM2 ADM1 Analog Input Channel Selection 0 0 0 ANI0 0 0 1 ANI1 0 1 0 ANI2 0 1 1 ANI3 1 0 0 ANI4 1 0 1 ANI5 1 1 0 ANI6 1 1 1 ANI7 FR1 FR0 A D Conversion Time SelectionNote 1 When operated at When operated at When operated at fX 10 0 MHz fX 8 38 M...

Page 253: ...ch is set for analog input with ADIS 2 On chip pull up resistor is not used for the channels set for analog input with ADIS irrespective of the value of bit 1 PUO1 of the pull up resistor option register Figure 14 3 A D Converter Input Select Register Format Symbol 7 6 5 4 3 2 1 0 Address When Reset R W ADIS 0 0 0 0 ADIS3 ADIS2 ADIS1 ADIS0 FF84H 00H R W ADIS3 ADIS2 ADIS1 ADIS0 Number of Analog Inp...

Page 254: ...or string voltage tap and analog input is compared with a voltage comparator If the analog input is larger than 1 2 AVREF the MSB of SAR remains set If the input is smaller than 1 2 AVREF the MSB is reset 7 Next bit 6 of SAR is automatically set and the operation proceeds to the next comparison In this case the series resistor string voltage tap is selected according to the preset value of bit 7 a...

Page 255: ...reset 0 by software If a write to the ADM is performed during an A D conversion operation the conversion operation is initialized and if the CS bit is set 1 conversion starts again from the beginning After RESET input the value of ADCR is undefined Conversion Time Sampling Time A D Converter Operation Sampling A D Conversion SAR Undefined 80H C0H or 40H Conversion Result ADCR INTAD Conversion Resu...

Page 256: ...AVREF or AVREF AVREF ADCR 0 5 VIN ADCR 0 5 256 256 where INT Function which returns integer parts of value in parentheses VIN Analog input voltage AVREF AVREF pin voltage ADCR A D conversion result register ADCR value Figure 14 5 shows the relationship between the analog input voltage and the A D conversion result Figure 14 5 Relationship between Analog Input Voltage and A D Conversion Result 255 ...

Page 257: ...arts on the voltage applied to the analog input pins specified with bits 1 to 3 ADM1 to ADM3 of ADM Upon termination of the A D conversion the conversion result is stored in the A D conversion result register ADCR and the interrupt request signal INTAD is generated After one A D conversion operation is started and terminated another operation is not started until a new external trigger signal is i...

Page 258: ...d and terminated the next A D conversion operation starts immediately The A D conversion operation continues repeatedly until new data is written to ADM If data with CS set to 1 is written to ADM again during A D conversion the converter suspends its A D conversion operation and starts A D conversion on the newly written data If data with CS set to 0 is written to ADM during A D conversion the A D...

Page 259: ...me this current must be cut in order to minimize the overall system power dissipation In this example the power dissipation can be reduced if a low level is output to the output port in the standby mode However the actual AVREF voltage is not so accurate and accordingly the converted value is not accurate and should be used for relative comparison only Figure 14 8 Example of Method of Reducing Pow...

Page 260: ...log input should be specified to the input mode When A D conversion is performed with any of pins ANI0 to ANI7 selected be sure not to execute a PORT1 input instruction while conversion is in progress as this may reduce the conversion resolution Also if digital pulses are applied to a pin adjacent to the pin in the process of A D conversion the expected A D conversion value may not be obtainable d...

Page 261: ...fer to Figure 14 10 When the A D conversion is stopped the ADIF must be cleared before restarting Figure 14 10 A D Conversion End Interrupt Request Generation Timing 7 AVDD pin The AVDD pin is the analog circuit power supply pin and supplies power to the input circuits of ANI0 P10 to ANI7 P17 Therefore be sure to apply the voltage at the same level as VDD as shown in Figure 14 11 even in an applic...

Page 262: ...www DataSheet4U com CHAPTER 14 A D CONVERTER 262 MEMO ...

Page 263: ...und on a board High speed serial interface to be complianced with the NEC standard bus format Address and command information onto the serial bus 2 wire serial I O SCK0 SB0 or Enables to configure serial bus with two signal lines SB1 thus even when connect to some microcontrollers the number of ports can be cut and reduced the wiring and drawing around on a board Enables to cope with any data tran...

Page 264: ...ith peripheral I O devices or display controllers which incorporate a conventional synchronous clocked serial interface as is the case with the 75X XL 78K and 17K series 3 SBI serial bus interface mode MSB first This mode is used for 8 bit data transfer with two or more devices using two lines of serial clock SCK0 and serial data bus SB0 or SB1 See Figure 15 1 The SBI mode complies with the NEC se...

Page 265: ...s of serial clock SCK0 and serial data bus SB0 or SB1 This mode enables to cope with any one of the possible data transfer formats by controlling the SCK0 level and the SB0 or SB1 output level Thus the handshake line previously necessary for connection of two or more devices can be removed resulting in an increased number of available input output ports SCK0 Master CPU SB0 VDD Slave CPU1 SCK0 SB0 ...

Page 266: ...www DataSheet4U com CHAPTER 15 SERIAL INTERFACE CHANNEL 0 µPD78014 Subseries 266 Figure 15 2 Serial Bus Configuration Example with 2 Wire Serial I O VDD VDD Master CPU Slave SCK0 SB0 SB1 SCK0 SB0 SB1 ...

Page 267: ...ration Item Configuration Register Serial I O shift register 0 SIO0 Slave address register SVA Control register Timer clock select register 3 TCL3 Serial operating mode register 0 CSIM0 Serial bus interface control register SBIC Interrupt timing specify register SINT Port mode register 2 PM2 Note Note Refer to Figure 6 6 P20 P21 P23 to P26 Block Diagrams µPD78014 Subseries and Figure 6 7 P22 and P...

Page 268: ...atch Selector Selector P26 Output Latch P27 Output Latch Slave Address Register SVA SVAM Match Serial I O Shift Register 0 SIO0 Bus Release Command Acknowledge Detector Serial Clock Counter Serial Clock Control Circuit CSIM00 CSIM01 Serial Bus Interface Control Register BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT CLR SET D Q ACKD CMDD RELD Busy Acknowledge Output Circuit WUP Interrupt Request Signal G...

Page 269: ...register does not be used in the 3 wire serial I O mode The master device outputs a slave address for selection of a particular slave device to the connected slave device These two data the slave address output from the master device and the SVA value are compared with an address comparator If they match the slave device has been selected In that case bit 6 COI of serial operating mode register 0 ...

Page 270: ...nal generation It generates the interrupt request signal in the following cases In the 3 wire serial I O mode and 2 wire serial I O mode This circuit generates an interrupt request signal every eight serial clocks In the SBI mode When WUPNote is 0 Generates an interrupt request signal every eight serial clocks When WUPNote is 1 Generates an interrupt request signal when the serial I O shift regist...

Page 271: ...y manipulation instruction RESET input sets TCL3 to 88H Remark TCL3 has functions to set the serial clock of serial interface channel 1 besides setting the serial clock of serial interface channel 0 2 Serial operating mode register 0 CSIM0 See Figure 15 5 This register sets serial interface channel 0 serial clock operating mode operation enable stop wake up function and displays the address compar...

Page 272: ... 28 39 1 kHz 1 1 0 1 fX 29 19 5 kHz Other than above Setting prohibited TCL37 TCL36 TCL35 TCL34 Serial Interface Channel 1 Serial Clock Selection 0 1 1 0 fX 22 Note 0 1 1 1 fX 23 1 25 MHz 1 0 0 0 fX 24 625 kHz 1 0 0 1 fX 25 313 kHz 1 0 1 0 fX 26 156 kHz 1 0 1 1 fX 27 78 1 kHz 1 1 0 0 fX 28 39 1 kHz 1 1 0 1 fX 29 19 5 kHz Other than above Setting prohibited Note Can be set only when the main system...

Page 273: ...rain CMOS input input output output Note 3 Note 3 2 wire MSB P25 SB1 SCK0 1 1 0 0 0 0 1 serial I O CMOS N ch open drain N ch open mode input output input output drain Note 3 Note 3 SB0 P26 input output 1 0 0 0 1 N ch open drain CMOS input output input output R W WUP Wake up Function ControlNote 4 0 Interrupt request signal generation with each serial transfer in any mode 1 Interrupt request signal...

Page 274: ... 0 After SO latch clearance automatically cleared to 0 Also cleared to 0 when CSIE0 0 R RELD Bus Release Detection Clear Conditions RELD 0 Set Conditions RELD 1 When transfer start instruction is executed When bus release signal REL is detected If SIO0 and SVA values do not match in address reception When CSIE0 0 When RESET input is applied Symbol 7 6 5 4 3 2 1 0 Address When Reset R W SBIC BSYE A...

Page 275: ... synchronization with the falling edge of SCK0 clock of transfer immediately after execution of the instruction to be set to 1 automatically output when ACKE 1 However not automatically cleared to 0 after acknowledge signal output R ACKD Acknowledge Detection Clear Conditions ACKD 0 Set Conditions ACKD 1 At the falling edge of SCK0 immediately after the When acknowledge signal ACK is detected at t...

Page 276: ...SVAM 0 0 0 0 FF63H 00H R WNote 1 R W SVAM SVA Bit to be Used as Slave Address 0 Bit 0 to Bit 7 1 Bit 1 to Bit 7 R W SIC INTCSI0 Interrupt Factor SelectionNote 2 0 CSIIF0 is set 1 upon termination of serial channel 0 transfer 1 CSIIF0 is set 1 upon bus release detection termination of serial interface channel R CLD SCK0 P27 Pin LevelNote 3 0 Low Level 1 High Level Notes 1 Bit 6 CLD is a Read Only b...

Page 277: ...stop mode 3 wire serial I O mode SBI mode 2 wire serial I O mode 15 4 1 Operation stop mode Serial transfer is not carried out in the operation stop mode Thus power dissipation can be reduced The serial I O shift register 0 SIO0 does not carry out shift operation either and thus it can be used as normal 8 bit register In the operation stop mode the P25 SI0 SB0 P26 SO0 SB1 and P27 SCK0 pins can be ...

Page 278: ...clocked serial interface as is the case with the 75X XL 78K and 17K series Communication is carried out with three lines of serial clock SCK0 serial output SO0 and serial input SI0 1 Register setting The 3 wire serial I O mode is set with the serial operating mode register 0 CSIM0 and serial bus interface control register SBIC a Serial operating mode register 0 CSIM0 CSIM0 is set with a 1 bit or 8...

Page 279: ...I0Note 2 SO0 SCK0 1 serial I O LSB Input CMOS CMOS mode output input output 1 0 SBI mode Refer to 15 4 3 SBI mode operation 1 0 2 wire serial I O mode Refer to 15 4 4 2 wire serial I O mode operation R W WUP Wake up Function ControlNote 3 0 Interrupt request signal generation with each serial transfer in any mode 1 Interrupt request signal generation when the address received after bus release whe...

Page 280: ...00H R W RELT When RELT 1 SO latch is set to 1 After SO latch setting automatically cleared to 0 Also cleared to 0 when CSIE0 0 R W CMDT When CMDT 1 SO latch is cleared to 0 After SO latch clearance automatically cleared to 0 Also cleared to 0 when CSIE0 0 Symbol 7 6 5 4 3 2 1 0 Address When Reset R W SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT FF61H 00H R W CSIE0 Bit 7 of the serial operating mod...

Page 281: ...pon termination of 8 bit transfer SIO0 operation stops automatically and the interrupt request flag CSIIF0 is set Figure 15 8 3 Wire Serial I O Mode Timings The SO0 pin serves for CMOS output and generates the SO0 latch status Thus the SO0 pin output status can be manipulated by setting bit 0 RELT and bit 1 CMDT of the serial bus interface control register SBIC However do not carry out this manipu...

Page 282: ... bus As shown in the figure MSB LSB can be read written in inverted form MSB LSB switching as the start bit can be specified with bit 2 CSIM02 of the serial operating mode register 0 CSIM0 Figure 15 10 Circuit of Switching in Transfer Bit Order Start bit switching is realized by switching the bit order for data write to SIO0 The SIO0 shift order remains unchanged Thus switch the MSB LSB start bit ...

Page 283: ...he single master high speed serial bus Thus when making up a serial bus with two or more microcontrollers and peripheral ICs the number of ports to be used and the number of wires on the board can be decreased The master device can output to the serial data bus of the slave device addresses for selection of the serial communication target device commands to instruct the target device and actual da...

Page 284: ...e master CPU slave CPU a pull up resistor is necessary for the serial clock line SCK0 as well because serial clock line SCK0 input output switching is carried out asynchronously between the master and slave CPUs Master CPU SCK0 SB0 SB1 Serial Clock Serial Data Bus VDD SB0 SB1 Slave CPU Address 1 Slave CPU Address 2 Slave IC Address N SCK0 SB0 SB1 SCK0 SB0 SB1 SCK0 ...

Page 285: ...ds and data b Chip select function by address transmission The master executes slave chip selection by address transmission c Wake up function The slave can easily judge address reception chip select judgment with the wake up function which can be set reset by software When the wake up function is set the interrupt request signal INTCSI0 is generated upon reception of a match address Thus when com...

Page 286: ... BUSY is output by the slave signal ACK can be output by either the master or slave device normally the 8 bit data receiver outputs Serial clocks continue to be output by the master device from 8 bit data transfer start to BUSY reset Address Transfer SB0 SB1 8 9 Bus Release Signal Address A7 A0 Command Transfer Command Signal SB0 SB1 C7 C0 READY Data Transfer 8 9 SB0 SB1 D7 D0 READY SCK0 SCK0 SCK0...

Page 287: ...e determined as the bus release signal even if data is sent Therefore perform wiring carefully b Command signal CMD The command signal is generated when the SCK0 line is in high level a serial clock is not output and the SB0 SB1 line changes from high level to low level The command signal is output by the master Figure 15 14 Command Signal SCK0 SB0 SB1 H SCK0 SB0 SB1 H The command signal indicates...

Page 288: ... slave detects the condition and checks by hardware if 8 bit data matches its specified number the slave address When 8 bit data matches the slave address which means the slave is selected the slave communicates with the master until the master instructs disconnection Figure 15 16 Slave Selection with Address SCK0 SB0 SB1 1 2 3 4 5 6 7 8 A7 A6 A5 A4 A3 A2 A1 A0 Address Command Signal Bus Release S...

Page 289: ...address Figure 15 17 Command Figure 15 18 Data 8 bit data following the command signal is defined as a command 8 bit data wihtout the command signal is defined as data How to use the command and data can be determined based on communication specifications SCK0 SB0 SB1 1 2 3 4 5 6 7 8 C7 C6 C5 C4 C3 C2 C1 C0 Command Command Signal SCK0 SB0 SB1 1 2 3 4 5 6 7 8 D7 D6 D5 D4 D3 D2 D1 D0 Data ...

Page 290: ...ates the READY state The acknowledge signal is a one shot pulse synchronous with SCK0 falling whose position can be synchronized with SCK0 in any clock The sending side that has transferred 8 bit data checks if the acknowledge signal has been sent back by the receiving side If this signal is not sent back by the slave device for a period after data sending this means that the data sent has not bee...

Page 291: ...rminates automatically to output the serial clock SCK0 when the busy signal is cleared The master can start subsequent transmissions when the busy signal is cleared and changes to the ready state Caution In the SBI mode the BUSY signal is output until the falling of the next serial clock after the BUSY release indication If WUP 1 is set by mistake during this period BUSY will not be released Thus ...

Page 292: ... 0 1 N ch open drain CMOS input input output output 1 1 2 wire serial I O mode Refer to 15 4 4 2 wire serial I O mode operation R W WUP Wake up Function ControlNote 3 0 Interrupt request signal generation with each serial transfer in any mode 1 Interrupt request signal generation when the address received after bus release when CMDD RELD 1 matches the slave address register SVA data when SBI mode ...

Page 293: ...ecuted When bus release signal REL is detected If SIO0 and SVA values do not match in address reception only if WUP 1 When CSIE0 0 When RESET input is applied R CMDD Command Detection Clear Conditions CMDD 0 Set Conditions CMDD 1 When transfer start instruction is executed When command signal CMD is detected When bus release signal REL is detected When CSIE0 0 When RESET input is applied R W ACKT ...

Page 294: ...ut R ACKD Acknowledge Detection Clear Conditions ACKD 0 Set Conditions ACKD 1 At the falling edge of SCK0 clock immediately after the When acknowledge signal ACK is detected at the busy mode has been released when a transfer start rising edge of SCK0 clock after completion of transfer instruction is executed When CSIE0 0 When RESET input is applied R W BSYENote Synchronizing Busy Signal Output Con...

Page 295: ... to set bits 0 to 3 to 0 Remark SVA Slave address register CSIIF0 Interrupt request flag supports the INTCSI0 CSIE0 Bit 7 of the serial operating mode register 0 CSIM0 R W SVAM SVA Bit to be Used as Slave Address 0 Bits 0 to 7 1 Bits 1 to 7 R W SIC INTCSI0 Interrupt Factor SelectionNote 2 0 CSIIF0 is set 1 upon termination of serial channel 0 transfer 1 CSIIF0 is set 1 upon bus release detection R...

Page 296: ... 4 lists various signals in SBI Figure 15 21 RELT CMDT RELD and CMDD Operations Master Figure 15 22 RELD and CMDD Operations Slave SIO0 SCK0 SB0 SB1 RELT CMDT RELD CMDD Slave address write to SIO0 Transfer Start Instruction SIO0 SCK0 SB0 SB1 RELD CMDD Write FFH to SIO0 Transfer start instruction Transfer start instruction A7 A6 A1 A0 Slave address 1 2 7 8 9 A7 A6 A1 A0 ACK READY When addresses mat...

Page 297: ...HANNEL 0 µPD78014 Subseries 297 Figure 15 23 ACKT Operation Caution Do not set ACKT before termination of transfer SCK0 SB0 SB1 ACKT D2 D1 D0 ACK ACK signal is output a period of one clock immediately after setting 6 7 8 9 When set during this period ...

Page 298: ...1 D0 ACK ACK signal is output at 9th clock When ACKE 1 at this point 1 2 7 8 9 SCK0 SB0 SB1 ACKE D2 D1 D0 ACK ACK signal is output a period of one clock immediately after setting If set during this period and ACKE 1 at the falling edge of the next SCK0 6 7 8 9 SCK0 SB0 SB1 ACKE D7 D6 D2 D1 D0 ACK signal is not output When ACKE 0 at this point 1 2 7 8 9 SCK0 SCK0 SB0 SB1 ACKE D2 D1 D0 If set and cl...

Page 299: ...transfer start is instructed in BUSY SIO0 SCK0 SB0 SB1 ACKD Transfer Start Instruction Transfer Start 6 7 8 9 D2 D1 D0 ACK SIO0 SCK0 SB0 SB1 ACKD Transfer Start Instruction Transfer Start 6 7 8 9 D2 D1 D0 ACK SIO0 SCK0 SB0 SB1 ACKD Transfer Start Instruction 6 7 8 9 D2 D1 D0 ACK BUSY D7 D6 SCK0 SB0 SB1 6 7 8 9 D2 D1 D0 ACK BUSY BSYE When BSYE 1 at this point Reset is performed during this period a...

Page 300: ...aster Low level signal to be 1 ACKE 1 ACKD set Completion of reception signal ACK slave output to SB0 SB1 2 ACKT set during one clock period of SCK0 after completion of serial reception Busy signal Slave Synchronous BUSY signal BSYE 1 Serial receive disable BUSY Low level signal to be because of processing output to SB0 SB1 following Acknowledge signal Ready signal Slave High level signal to be 1 ...

Page 301: ...clock to serial data bus data ACK signal instruction for of SCK0 Note 1 synchronization BUSY data write to SIO0 signal etc Address serial transfer command data are start instruction transferred with the first Note 2 eight synchronous clocks Address Master 8 bit data to be transferred Address value of slave A7 to A0 in synchronization with device on the serial bus SCK0 after output of REL and CMD s...

Page 302: ...tion The serial clock pin SCK0 and serial data bus pin SB0 SB1 have the following configurations a SCK0 Serial clock input output pin 1 Master CMOS and push pull output 2 Slave Schmitt input b SB0 SB1 Serial data input output dual function pin Both master and slave devices have an N ch open drain output and a Schmitt input Because the serial data bus line has an N ch open drain output an external ...

Page 303: ...ress to be generated with WUP 1 is normally used Thus execute selection non selection detection by slave address when WUP 1 2 When detecting selection non selection without the use of interrupt request with WUP 0 do so by means of transmission reception of the command preset by program instead of using the address match detection method 7 Error detection In the SBI mode the serial bus SB0 SB1 stat...

Page 304: ...een determined commands and data are transmitted received and serial communication is realized between the master and slave devices Figures 15 28 to 15 31 show data communication timing charts Shift operation of the serial I O shift register 0 SIO0 is carried out at the falling edge of serial clock SCK0 Transmit data is latched into the SO0 latch and is output with MSB set as the first bit from th...

Page 305: ...ission INTCSI0 Generation ACKD Set SCK0 Stop 1 2 3 4 5 6 7 8 9 A7 A6 A5 A4 A3 A2 A1 A0 BUSY READY WUP 0 ACKT Set BUSY Clear CMDD Set CMDD Clear CMDD Set RELD Set Serial Reception INTCSI0 Generation ACK Output BUSY Output BUSY Clear When SVA SIO0 Program Processing Hardware Operation SCK0 Pin SB0 SB1 Pin Program Processing Hardware Operation CMDT Set RELT Set CMDT Set Write to SIO0 Interrupt Servic...

Page 306: ...ver Serial Transmission INTCSI0 Generation ACKD Set SCK0 Stop 1 2 3 4 5 6 7 8 9 C7 C6 C5 C4 C3 C2 C1 C0 BUSY READY Command analysis ACKT Set BUSY Clear CMDD Set Serial Reception INTCSI0 Generation ACK Output BUSY Output BUSY Clear Program Processing Hardware Operation SCK0 Pin SB0 SB1 Pin Program Processing Hardware Operation CMDT Set Write to SIO0 Interrupt Servicing Preparation for the Next Seri...

Page 307: ... Processing Receiver Serial Transmission INTCSI0 Generation ACKD Set SCK0 Stop 1 2 3 4 5 6 7 8 9 D7 D6 D5 D4 D3 D2 D1 D0 BUSY READY ACKT Set BUSY Clear Serial Reception INTCSI0 Generation ACK Output BUSY Output BUSY Clear Program Processing Hardware Operation SCK0 Pin SB0 SB1 Pin Program Processing Hardware Operation Write to SIO0 Interrupt Servicing Preparation for the Next Serial Transfer ACK Da...

Page 308: ... 3 4 5 6 7 8 9 D7 D6 D5 D4 D3 D2 D1 D0 BUSY READY Program Processing Hardware Operation SCK0 Pin SB0 SB1 Pin Program Processing Hardware Operation ACK Data FFH Write to SIO0 Receive Data Processing Serial Reception INTCSI0 Generation ACKT Set SCK0 Stop 1 2 ACKD Set BUSY Clear Serial Reception INTCSI0 Generation BUSY Output BUSY Clear Write to SIO0 SIO0 Read FFH Write to SIO0 ACK Output Serial Rece...

Page 309: ... output be sure to carry out the following settings before serial transfer of the 1st byte after RESET input 1 Set the P25 and P26 output latches to 1 2 Set bit 0 RELT of the serial bus interface control register SBIC to 1 3 Reset the P25 and P26 output latches from 1 to 0 10 Distinction method of slave busy state When device is in the master mode follow the procedure below to judge whether slave ...

Page 310: ...rol register SBIC to 1 3 Reset the P25 and P26 output latches from 1 to 0 e The bus release signal or the command signal is acknowledged when the SCK0 line is in high level and the SB0 SB1 line changes from low level to high level or from high level to low level Thus if the timing at which bus changes deviates due to effects such as board capacity it may be determined as the bus release signal or ...

Page 311: ...e serial I O mode is set with the serial operating mode register 0 CSIM0 the serial bus interface control register SBIC and the interrupt timing specification register SINT a Serial operating mode register 0 CSIM0 CSIM0 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIM0 to 00H ...

Page 312: ...N ch open drain N ch open input output input output drain Note 2 Note 2 SB0 P26 input output 1 0 0 0 1 N ch open drain CMOS input output input output R W WUP Wake up Function ControlNote 3 0 Interrupt request signal generation with each serial transfer in any mode 1 Interrupt request signal generation when the address received after bus release when CMDD RELD 1 matches the slave address register S...

Page 313: ...00H R W RELT When RELT 1 SO latch is set to 1 After SO latch setting automatically cleared to 0 Also cleared to 0 when CSIE0 0 R W CMDT When CMDT 1 SO latch is cleared to 0 After SO latch clearance automatically cleared to 0 Also cleared to 0 when CSIE0 0 Symbol 7 6 5 4 3 2 1 0 Address When Reset R W SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT FF61H 00H R W CSIE0 Bit 7 of the serial operating mod...

Page 314: ... transfer 1 CSIIF0 is set 1 upon bus release detection R CLD SCK0 P27 Pin LevelNote 2 0 Low Level 1 High Level Notes 1 Bit 6 CLD is a Read Only bit 2 When CSIE0 0 CLD becomes 0 Caution Be sure to set bits 0 to 3 to 0 Remark CSIIF0 Interrupt request flag supports the INTCSI0 CSIE0 Bit 7 of the serial operating mode register 0 CSIM0 c Interrupt timing specification register SINT SINT is set with a 1...

Page 315: ...lly and the interrupt request flag CSIIF0 is set Figure 15 33 2 Wire Serial I O Mode Timings The SB0 or SB1 pin specified for the serial data bus serves for N ch open drain input output and thus it must be externally pulled up Because it is necessary to be set to high impedance the N ch open drain output for data reception write FFH to SIO0 in advance The SB0 or SB1 pin generates the SO0 latch sta...

Page 316: ...ing two conditions are satisfied Serial interface channel 0 operation control bit CSIE0 1 Internal serial clock is stopped or SCK0 is at high level after 8 bit serial transfer Cautions 1 If CSIE0 is set to 1 after data write to SIO0 transfer does not start 2 Because the N ch open drain output must be set to high impedance for data reception write FFH to SIO0 in advance Upon termination of 8 bit tr...

Page 317: ...ed to have been carried out If it is 0 a transmit error is judged to have occurred 15 4 5 SCK0 P27 pin output manipulation Because the SCK0 P27 pin incorporates an output latch static output is also possible by software in addition to normal serial clock output P27 output latch manipulation enables any value of SCK0 to be set by software SI0 SB0 and SO0 SB1 pin to be controlled with bit 0 RELD or ...

Page 318: ...www DataSheet4U com CHAPTER 15 SERIAL INTERFACE CHANNEL 0 µPD78014 Subseries 318 MEMO ...

Page 319: ... 0 and 1 Serial Transfer Mode Channel 0 Channel 1 3 wire serial I O Clock selection fX 22Note fX 23 fX 24 fX 25 fX 26 fX 27 fX 28 fX 29 external clock TO2 output clock Transfer method MSB LSB switchable as the start bit MSB LSB switchable as the start bit Automatic transmit receive function Transfer end Serial interface channel transfer end Serial interface channel transfer end flag interrupt requ...

Page 320: ...s before SBI mode SCK0 SB0 or Enables configuration of serial bus with two signal SB1 lines thus even when connected to some microcontrollers the number of ports can be cut and wiring and routing on a board can be reduced High speed serial interface compliant with the NEC standard bus format Address and command information onto the serial bus 2 wire serial SCK0 SB0 or Enables configuration of seri...

Page 321: ...ction of peripheral I O units and display controllers which incorporate a conventional synchronous clocked serial interface as is the case with the 75X XL 78K and 17K series 3 SBI serial bus interface mode MSB first This mode is used for 8 bit data transfer with two or more devices using two lines of serial clock SCK0 and serial data bus SB0 or SB1 see Figure 16 1 The SBI mode complies with the NE...

Page 322: ...o lines of the serial clock SCK0 and serial data bus SB0 or SB1 This mode supports any one of the possible data transfer formats by controlling the SCK0 level and the SB0 or SB1 output level Thus the handshake line previously necessary for connecting two or more devices can be removed resulting in an increased number of available input output ports SCK0 Master CPU SB0 VDD Slave CPU1 SCK0 SB0 Slave...

Page 323: ...www DataSheet4U com CHAPTER 16 SERIAL INTERFACE CHANNEL 0 µPD78014Y Subseries 323 Figure 16 2 Serial Bus Configuration Example with 2 Wire Serial I O VDD VDD Master CPU Slave SCK0 SB0 SB1 SCK0 SB0 SB1 ...

Page 324: ...data bus SDA0 or SDA1 This mode complies with the NEC I2C bus format In this mode the transmitter outputs three kinds of data onto the serial data bus start condition data and stop condition The receiver automatically detects the received data by hardware Figure 16 3 Serial Bus Configuration Example Using I2C Bus VDD VDD Master CPU Slave CPU1 Slave CPU2 Slave CPUn SCL SDA0 SDA1 SCL SDA0 SDA1 SCL S...

Page 325: ...ation Item Configuration Register Serial I O shift register 0 SIO0 Slave address register SVA Control register Timer clock select register 3 TCL3 Serial operating mode register 0 CSIM0 Serial bus interface control register SBIC Interrupt timing specify register SINT Port mode register 2 PM2 Note Note Refer to Figure 6 8 P20 P21 P23 to P26 Block Diagrams µPD78074Y Subseries and Figure 6 9 P22 and P...

Page 326: ...ctor Selector P26 Output Latch P27 Output Latch Slave Address Register SVA SVAM Match Serial I O Shift Register 0 SIO0 Bus Release Command Acknowledge Detector Serial Clock Counter Serial Clock Control Circuit CSIM00 CSIM01 Serial Bus Interface Control Register BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT CLR SET D Q ACKD CMDD RELD Busy Acknowledge Output Circuit WUP Internal Bus Interrupt Request Sign...

Page 327: ...ction of a slave device to the serial bus SVA is set with an 8 bit memory manipulation instruction This register does not be used in the 3 wire serial I O mode The master device outputs a slave address for selection of a particular slave device to the connected slave device These two data the slave address output from the master device and the SVA value are compared with an address comparator If t...

Page 328: ...l clock supply to the serial I O shift register 0 SIO0 When the internal system clock is used the circuit also controls clock output to the SCK0 SCL P27 pin 6 Interrupt request signal generator This circuit controls interrupt request signal generation It generates the interrupt request signal by setting bits 0 1 WAT0 WAT1 of the interrupt timing specify register SINT and bit 5 WUP of the serial op...

Page 329: ...oftware ACK information is generated by the receiving side thus ACKE should be set to 0 disable 1 1 0 An interrupt request signal is generated each time 9 serial clocks are counted 9 clock wait ACK information is generated by the receiving side thus ACKE should be set to 0 disable Other than above Setting prohibited I2 C bus mode receive 0 1 0 0 An interrupt request signal is generated each time 8...

Page 330: ...his register sets serial interface channel 0 serial clock operating mode operation enable stop wake up function and displays the address comparator match signal CSIM0 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIM0 to 00H Caution Do not switch the operation mode 3 wire serial I O 2 wire serial I O SBI I2C bus during the serial interface channel 0 operation enabl...

Page 331: ...Hz fX 26 156 kHz 1 0 1 1 fX 211 4 9 kHz fX 27 78 1 kHz 1 1 0 0 fX 212 2 4 kHz fX 28 39 1 kHz 1 1 0 1 fX 213 1 2 kHz fX 29 19 5 kHz Other than above Setting prohibited TCL37 TCL36 TCL35 TCL34 Serial Interface Channel 1 Serial Clock Seletion 0 1 1 0 fX 22 Note 0 1 1 1 fX 23 1 25 MHz 1 0 0 0 fX 24 625 kHz 1 0 0 1 fX 25 313 kHz 1 0 1 0 fX 26 156 kHz 1 0 1 1 fX 27 78 1 kHz 1 1 0 0 fX 28 39 1 kHz 1 1 0 ...

Page 332: ... input output drain Note 4 Note 4 Mode SB0 SDA0 P26 input output 1 0 0 0 1 N ch open drain CMOS input output input output R W WUP Wake up Function ControlNote 5 0 Interrupt request signal generation with each serial transfer in any mode 1 Interrupt request signal generation when the address received after bus release when CMDD RELD 1 in the SBI mode CMDD 1 in the I2 C bus mode matches the slave ad...

Page 333: ...ave address register SVA not equal to serial I O shift register 0 SIO0 data 1 Slave address register SVA equal to serial I O shift register 0 SIO0 data R W CSIE0 Serial Interface Channel 0 Operation Control 0 Operation stopped 1 Operation enabled Figure 16 6 Serial Operating Mode Register 0 Format 2 2 Note When CSIE0 0 COI becomes 0 ...

Page 334: ...DD 0 Set Conditions CMDD 1 When transfer start instruction is executed When command signal CMD is detected in the SBI mode When bus release signal REL is detected When stop condition is detected in the I2 C mode When stop condition is detected in the I2 C bus mode When CSIE0 0 When RESET input is applied R W ACKT When the SBI mode is used acknowledge signal is output in synchronization with the fa...

Page 335: ...to 0 after acknowledge signal output Used in reception with 9 clock wait mode selected R ACKD Acknowledge Detection Clear Conditions ACKD 0 Set Conditions ACKD 1 At the falling edge of SCK0 clock immediately after the When acknowledge signal is detected at the rising busy mode has been released when a transfer start edge of SCK0 SCL clock after completion of transfer instruction is executed Upon e...

Page 336: ...t state after output In the case of slave device makes SCL output low to request waits pulses are input R W WREL Wait State Cancellation Control 0 Wait state has been cancelled 1 Cancels wait state Automatically cleared to 0 when the state is cancelled Used to cancel wait state by means of WAT0 and WAT1 R W CLC Clock Level ControlNote 2 0 Used in I2 C bus mode Make output level of SCL pin low unle...

Page 337: ...ransfer 1 CSIIF0 is set to 1 upon stop condition detection in the I2 C bus mode or termination of serial interface in the SBI mode R CLD SCK0 SCL P27 Pin LevelNote 2 0 Low level 1 High level Figure 16 8 Interrupt Timing Specification Register Format 2 2 Notes 1 When using wake up function set SIC to 0 2 When CSIE0 0 CLD becomes 0 Remark SVA Slave address register CSIIF0 Interrupt request flag supp...

Page 338: ...erial I O mode SBI mode 2 wire serial I O mode I2C Inter IC bus mode 16 4 1 Operation stop mode Serial transfer is not carried out in the operation stop mode Thus power dissipation can be reduced The serial I O shift register 0 SIO0 does not carry out shift operation either and thus it can be used as normal 8 bit register In the operation stop mode the P25 SI0 SB0 SDA0 P26 SO0 SB1 SDA1 and P27 SCK...

Page 339: ... clocked serial interface as is the case with the 75X XL 78K and 17K series Communication is carried out with three lines of serial clock SCK0 serial output SO0 and serial input SI0 1 Register setting The 3 wire serial I O mode is set with the serial operating mode register 0 CSIM0 and serial bus interface control register SBIC a Serial operating mode register 0 CSIM0 CSIM0 is set with a 1 bit or ...

Page 340: ...tput input output 1 0 SBI mode Refer to 16 4 3 SBI mode operation 1 1 2 wire serial I O mode Refer to 16 4 4 2 wire serial I O mode operation or I2 C bus mode Refer to 16 4 5 I2 C bus mode operation R W WUP Wake up Function ControlNote 3 0 Interrupt request signal generation with each serial transfer in any mode 1 Interrupt request signal generation when the address received after bus release when...

Page 341: ... register SBIC SBIC is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets SBIC to 00H R W RELT When RELT 1 SO latch is set to 1 After SO latch setting automatically cleared to 0 Also cleared to 0 when CSIE0 0 R W CMDT When CMDT 1 SO latch is cleared to 0 After SO latch clearance automatically cleared to 0 Also cleared to 0 when CSIE0 0 CSIE0 Bit 7 of the serial operating mo...

Page 342: ... Upon termination of 8 bit transfer SIO0 operation stops automatically and the interrupt request flag CSIIF0 is set Figure 16 9 3 Wire Serial I O Mode Timings The SO0 pin serves for CMOS output and generates the SO0 latch status Thus the SO0 pin output status can be manipulated by setting bit 0 RELT and bit 1 CMDT of the serial bus interface control register SBIC However do not carry out this mani...

Page 343: ...al bus As shown in the figure MSB LSB can be read written in inverted form MSB LSB switching as the start bit can be specified with bit 2 CSIM02 of the serial operating mode register 0 CSIM0 Figure 16 11 Circuit of Switching in Transfer Bit Order Start bit switching is realized by switching the bit order for data write to SIO0 The SIO0 shift order remains unchanged Thus switch the MSB LSB start bi...

Page 344: ...e single master high speed serial bus Thus when making up a serial bus with two or more microcomputers and peripheral ICs the number of ports to be used and the number of wires on the board can be decreased The master device can output to the serial data bus of the slave device addresses for selection of the serial communication target device commands to instruct the target device and actual data ...

Page 345: ...e master CPU slave CPU a pull up resistor is necessary for the serial clock line SCK0 as well because serial clock line SCK0 input output switching is carried out asynchronously between the master and slave CPUs Master CPU SCK0 SB0 SB1 Serial Clock Serial Data Bus VDD SB0 SB1 Slave CPU Address 1 Slave CPU Address 2 Slave IC Address N SCK0 SB0 SB1 SCK0 SB0 SB1 SCK0 ...

Page 346: ...ed into addresses commands and data b Chip select function by address transmission The master executes slave chip selection by address transmission c Wake up function The slave can easily judge address reception chip select judgment with the wake up function which can be set reset by software When the wake up function is set the interrupt request signal INTCSI0 is generated upon reception of a mat...

Page 347: ...e BUSY is output by the slave signal ACK can be output by either the master or slave device normally the 8 bit data receiver outputs Serial clocks continue to be output by the master device from 8 bit data transfer start to BUSY reset Address Transfer SB0 SB1 8 9 Bus Release Signal A7 A0 Command Transfer Command Signal SB0 SB1 C7 C0 READY Data Transfer 8 9 SB0 SB1 D7 D0 READY SCK0 SCK0 SCK0 ACK BU...

Page 348: ...e determined as the bus release signal even if data is sent Therefore perform wiring carefully b Command Signal CMD The command signal is generated when the SCK0 line is in high level a serial clock is not output and the SB0 SB1 line changes from high level to low level The command signal is output by the master Figure 16 15 Command Signal The command signal indicates that master will send the com...

Page 349: ...e slave detects the condition and checks by hardware if 8 bit data matches its specified number the slave address When 8 bit data matches the slave address which means the slave is selected the slave communicates with the master until the master instructs disconnection Figure 16 17 Slave Selection with Address SCK0 SB0 SB1 1 2 3 4 5 6 7 8 A7 A6 A5 A4 A3 A2 A1 A0 Address Command Signal Bus Release ...

Page 350: ...ess Figure 16 18 Command Figure 16 19 Data 8 bit data following the command signal is defined as a command 8 bit data without the command signal is defined as data How to use the command and data can be determined depending on the communication specifications SCK0 SB0 SB1 1 2 3 4 5 6 7 8 C7 C6 C5 C4 C3 C2 C1 C0 Command Command Signal SCK0 SB0 SB1 1 2 3 4 5 6 7 8 D7 D6 D5 D4 D3 D2 D1 D0 Data ...

Page 351: ... SCK0 in 9th clock Remark The broken line indicates the READY state The acknowledge signal is a one shot pulse synchronous with SCK0 falling whose position can be synchronized with SCK0 in any clock The sending side that has transferred 8 bit data checks if the acknowledge signal has been sent from the receiving side If this signal is not sent back from the slave device for a given period after da...

Page 352: ...tes automatically to output the serial clock SCK0 when the busy signal is cleared The master can start subsequent transmissions when the busy signal is cleared and changes to the ready state Caution In the SBI mode the BUSY signal is output until the falling of the next serial clock after the BUSY release indication If WUP 1 is set by mistake during this period BUSY will not be released Thus after...

Page 353: ...utput 1 1 2 wire serial I O mode Refer to 16 4 4 2 wire serial I O mode operation or I2 C bus mode Refer to 16 4 5 I2 C bus mode operation R W WUP Wake up Function ControlNote 3 0 Interrupt request signal generation with each serial transfer in any mode 1 Interrupt request signal generation when the address received after bus release when CMDD RELD 1 matches the slave address register SVA data whe...

Page 354: ...Bus Release Detection Clear Conditions RELD 0 Set Conditions RELD 1 When transfer start instruction is executed When bus release signal REL is detected in the SBI mode If SIO0 and SVA values do not match in address reception only if WUP 1 When CSIE0 0 When RESET input is applied R CMDD Command Detection Clear Conditions CMDD 0 Set Conditions CMDD 1 When transfer start instruction is executed When ...

Page 355: ...tion Clear Conditions ACKD 0 Set Conditions ACKD 1 In the SBI mode at the falling edge of SCK0 clock When acknowledge signal ACK is detected at the immediately after the busy mode has been released rising edge of SCK0 clock after completion of transfer when a transfer start instruction is executed When CSIE0 0 When RESET input is applied R W BSYENote Synchronizing Busy Signal Output Control 0 When...

Page 356: ... CSIIF0 is set 1 upon bus release detection in SBI mode R CLD SCK0 SCL P27 Pin LevelNote 3 0 Low Level 1 High Level c Interrupt timing specification register SINT SINT is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets SINT to 00H Notes 1 Bit 6 CLD is a Read Only bit 2 When using wake up function set SIC to 0 3 When CSIE0 0 CLD becomes 0 Caution Be sure to set bits 0 to ...

Page 357: ...16 5 lists various signals in SBI Figure 16 22 RELT CMDT RELD and CMDD Operations Master Figure 16 23 RELD and CMDD Operations Slave SIO0 SCK0 SB0 SB1 RELT CMDT RELD CMDD Slave address write to SIO0 Transfer Start Instruction SIO0 SCK0 SB0 SB1 RELD CMDD Write FFH to SIO0 Transfer start instruction Transfer start instruction A7 A6 A1 A0 Slave Address 1 2 7 8 9 A7 A6 A1 A0 ACK READY When addresses m...

Page 358: ...EL 0 µPD78014Y Subseries 358 Figure 16 24 ACKT Operation Caution Do not set ACKT before termination of transfer SCK0 SB0 SB1 ACKT D2 D1 D0 ACK ACK signal is output during a period of one clock immediately after setting 6 7 8 9 When set during this period ...

Page 359: ...D1 D0 ACK ACK signal is output at 9th clock When ACKE 1 at this point 1 2 7 8 9 SCK0 SB0 SB1 ACKE D2 D1 D0 ACK ACK signal is output a period of one clock immediately after setting If set during this period and ACKE 1 at the falling edge of the next SCK0 6 7 8 9 SCK0 SB0 SB1 ACKE D7 D6 D2 D1 D0 ACK signal is not output When ACKE 0 at this point 1 2 7 8 9 SCK0 SCK0 SB0 SB1 ACKE D2 D1 D0 If set and c...

Page 360: ...art is instructed in BUSY Figure 16 27 BSYE Operation SIO0 SCK0 SB0 SB1 ACKD Transfer Start Instruction Transfer Start 6 7 8 9 D2 D1 D0 ACK SIO0 SCK0 SB0 SB1 ACKD Transfer Start Instruction Transfer Start 6 7 8 9 D2 D1 D0 ACK SIO0 SCK0 SB0 SB1 ACKD Transfer Start Instruction 6 7 8 9 D2 D1 D0 ACK BUSY D7 D6 SCK0 SB0 SB1 6 7 8 9 D2 D1 D0 ACK BUSY BSYE When BSYE 1 at this point If reset during this p...

Page 361: ...d transmit data is a command Acknowledge Master Low level signal to be 1 ACKE 1 ACKD set Completion of reception signal ACK slave output to SB0 SB1 2 ACKT set during one clock period of SCK0 after completion of serial reception Busy signal Slave Synchronous BUSY signal BSYE 1 Serial receive disable BUSY Low level signal to be because of processing output to SB0 SB1 following acknowledge signal Rea...

Page 362: ...e of slave A7 to A0 in synchronization with device on the serial bus SCK0 after output of REL and CMD signals Address Master 8 bit data to be transferred Instruction messages to C7 to C0 in synchronization with the slave device SCK0 after output of only CMD signal without REL signal output Address Master 8 bit data to be transferred Numeric values to be D7 to D0 slave in synchronization with proce...

Page 363: ...bus line has an N ch open drain output an external pull up resistor is necessary Figure 16 28 Pin Configuration Caution Because the N ch open drain output must be set to high impedance at the time of data reception write FFH to the serial I O shift register 0 SIO0 in advance However when the wake up function specification bit WUP 1 the N ch open drain output will always be set to high impedance Th...

Page 364: ...address to be generated with WUP 1 is normally used Thus execute selection non selection detection by slave address when WUP 1 2 When detecting selection non selection without the use of interrupt request with WUP 0 do so by means of transmission reception of the command preset by program instead of using the address match detection method 7 Error detection In the SBI mode the serial bus SB0 SB1 s...

Page 365: ...been determined commands and data are transmitted received and serial communication is realized between the master and slave devices Figures 16 29 to 16 32 show data communication timing charts Shift operation of the serial I O shift register 0 SIO0 is carried out at the falling edge of serial clock SCK0 Transmit data is latched into the SO0 latch and is output with MSB set as the first bit from t...

Page 366: ...ission INTCSI0 Generation ACKD Set SCK0 Stop 1 2 3 4 5 6 7 8 9 A7 A6 A5 A4 A3 A2 A1 A0 BUSY READY WUP 0 ACKT Set BUSY Clear CMDD Set CMDD Clear CMDD Set RELD Set Serial Reception INTCSI0 Generation ACK Output BUSY Output BUSY Clear When SVA SIO0 Program Processing Hardware Operation SCK0 Pin SB0 SB1 Pin Program Processing Hardware Operation CMDT Set RELT Set CMDT Set Write to SIO0 Interrupt Servic...

Page 367: ...ver Serial Transmission INTCSI0 Generation ACKD Set SCK0 Stop 1 2 3 4 5 6 7 8 9 C7 C6 C5 C4 C3 C2 C1 C0 BUSY READY Command analysis ACKT Set BUSY Clear CMDD Set Serial Reception INTCSI0 Generation ACK Output BUSY Output BUSY Clear Program Processing Hardware Operation SCK0 Pin SB0 SB1 Pin Program Processing Hardware Operation CMDT Set Write to SIO0 Interrupt Servicing Preparation for the Next Seri...

Page 368: ...e Processing Receiver Serial Transmission INTCSI0 Generation ACKD Set SCK0 Stop 1 2 3 4 5 6 7 8 9 D7 D6 D5 D4 D3 D2 D1 D0 BUSY READY ACKT Set BUSY Clear Serial Reception INTCSI0 Generation ACK Output BUSY Output BUSY Clear Program Processing Hardware Operation SCK0 Pin SB0 SB1 Pin Program Processing Hardware Operation Write to SIO0 Interrupt Servicing Preparation for the Next Serial Transfer ACK D...

Page 369: ...3 4 5 6 7 8 9 D7 D6 D5 D4 D3 D2 D1 D0 BUSY READY Program Processing Hardware Operation SCK0 Pin SB0 SB1 Pin Program Processing Hardware Operation ACK Data FFH Write to SIO0 Receive Data Processing Serial Transmission INTCSI0 Generation ACKT Set SCK0 Stop 1 2 ACKD Set BUSY Clear Serial Reception INTCSI0 Generation BUSY Output BUSY Clear Write to SIO0 SIO0 Read FFH Write to SIO0 ACK Output Serial Re...

Page 370: ... not lost When the busy state is cleared and SB0 or SB1 input is set to the high level READY state transfer starts Upon termination of 8 bit transfer serial transfer automatically stops and the interrupt request flag CSIIF0 is set For pins which are to be used for data input output be sure to carry out the following settings before serial transfer of the 1st byte after RESET input 1 Set the P25 an...

Page 371: ... BUSY release indication If WUP 1 is set by mistake during this period BUSY will not be released Thus after releasing BUSY be sure to check that the SB0 SB1 has become high level before setting WUP 1 d For pins which are to be used for data input output be sure to carry out the following settings before serial transfer of the 1st byte after RESET input 1 Set the P25 and P26 output latches to 1 2 S...

Page 372: ...ta input output SB0 or SB1 Figure 16 33 Example of Serial Bus Configuration with 2 Wire Serial I O 1 Register setting The 2 wire serial I O mode is set with the serial operating mode register 0 CSIM0 the serial bus interface control register SBIC and the interrupt timing specification register SINT a Serial operating mode register 0 CSIM0 CSIM0 is set with a 1 bit or 8 bit memory manipulation inst...

Page 373: ...t output input output drain Note 2 Note 2 bus mode SB0 SDA0 P26 input output 1 0 0 0 1 N ch open drain CMOS input output input output R W WUP Wake up Function ControlNote 3 0 Interrupt request signal generation with each serial transfer in all modes 1 Interrupt request signal generation when the address received after bus release when CMDD RELD 1 when the SBI mode is used or when CMDD 1 when the I...

Page 374: ... 00H Symbol 7 6 5 4 3 2 1 0 Address When Reset R W SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT FF61H 00H R W R W RELT When RELT 1 SO latch is set to 1 After SO latch setting automatically cleared to 0 Also cleared to 0 when CSIE0 0 R W CMDT When CMDT 1 SO latch is cleared to 0 After SO latch clearance automatically cleared to 0 Also cleared to 0 when CSIE0 0 CSIE0 Bit 7 of the serial operating mo...

Page 375: ... WAT1 WAT0 FF63H 00H R WNote 1 R W SIC INTCSI0 Interrupt Factor Selection 0 CSIIF0 is set 1 upon termination of serial channel 0 transfer 1 CSIIF0 is set 1 upon bus release detection R CLD SCK0 SCL P27 Pin LevelNote 2 0 Low Level 1 High Level Notes 1 Bit 6 CLD is a Read Only bit 2 When CSIE0 0 CLD becomes 0 Caution Be sure to set bits 0 to 3 to 0 when 2 wire serial I O mode is used Remark CSIIF0 I...

Page 376: ...ically and the interrupt request flag CSIIF0 is set Figure 16 34 2 Wire Serial I O Mode Timings The SB0 or SB1 pin specified for the serial data bus serves for N ch open drain input output and thus it must be externally pulled up Because it is necessary to be set to high impedance the N ch open drain output for data reception write FFH to SIO0 in advance The SB0 or SB1 pin generates the SO0 latch ...

Page 377: ...8 bit transfer serial transfer automatically stops and the interrupt request flag CSIIF0 is set 5 Error detection In the 2 wire serial I O mode the serial bus SB0 SB1 status being transmitted is fetched into the destination device that is serial I O shift register 0 SIO0 Thus transmit error can be detected in the following way a Method of comparing SIO0 data before transmission to that after trans...

Page 378: ... I2C bus specification the master sends start condition data and stop condition signals to slave devices through the serial data bus Slave devices automatically detect and distinguish the type of signals due to the signal detection function incorporated as hardware This simplifies the application program to control I2C bus An example of a serial bus configuration is shown in Figure 16 36 This syst...

Page 379: ...peration Therefore CPUs other than the selected slave device on the I2C bus can perform independent operations during the serial communication d Acknowledge signal ACK control function The master device and a slave device send and receive acknowledge signals to confirm that the serial communication has been executed normally e Wait signal WAIT control function The slave device controls a wait sign...

Page 380: ...from the master device a Start condition When the SDA0 SDA1 pin level is changed from high to low while the SCL pin is high this transition is recognized as the start condition signal This start condition signal which is created using the SCL and SDA0 or SDA1 pins is output from the master device to slave devices to initiate a serial transfer See section 16 4 6 Cautions on use of I2C bus mode for ...

Page 381: ... device in which the data are a match becomes the communication partner and subsequently performs communication with the master device until the master device sends a start condition or stop condition signal Figure 16 39 Address c Transfer direction specification The 1 bit data that follows the 7 bit address data will be sent from the master device and it is defined as the transfer direction speci...

Page 382: ... the sending side device receives the acknowledge signal which means a successful data transfer it proceeds to the next processing If this signal is not sent back from the slave device this means that the data sent has not been received correctly by the slave device and therefore the master device outputs a stop condition signal to terminate subsequent transmissions Figure 16 41 Acknowledge Signal...

Page 383: ...leasing operation of slave devices see section 16 4 6 Cautions on use of I2C bus mode Figure 16 43 Wait Signal a Wait of 8 Clock Cycles b Wait of 9 Clock Cycles D2 D1 D0 ACK D7 Output by manipulating ACKT SCL of master device 6 7 8 9 1 3 2 4 D6 D5 D4 Slave device drives low though master device returns to Hi Z state No wait is inserted after 9th clock cycle and before master device starts next tra...

Page 384: ...2 outputNote 2 1 1 Clock specified with bits 0 to 3 of timer clock select register 3 TCL3 R W CSIM CSIM CSIM PM25 P25 PM26 P26 PM27 P27 Operating Start Bit SI0 SB0 SDA0 SO0 SBI SDA1 SCK0 SCL 04 03 02 Mode P25 Pin Function P26 Pin Function P27 Pin Function 0 3 wire serial I O mode Refer to 16 4 2 3 wire serial I O mode operation 1 0 SBI mode Refer to 16 4 3 SBI mode operation Note 3 Note 3 2 wire s...

Page 385: ...l transfer in all modes 1 Interrupt request signal generation when the address received after bus release when CMDD RELD 1 when the SBI mode is used or when CMDD 1 when the I2 C bus mode is used matches the slave address register SVA data in the SBI mode and the I2 C bus mode R COI Slave Address Comparison Result FlagNote 2 0 Slave address register SVA not equal to serial I O shift register 0 SIC0...

Page 386: ...ditions CMDD 0 Set Conditions CMDD 1 When transfer start instruction is executed When start condition is detected in the I2 C bus mode When stop condition is detected in the I2 C bus mode When CSIE0 0 When RESET input is applied R W ACKT When the I2 C bus mode is used SDA0 SDA1 is made low level until the next SCL falling edge immediately after execution of the set instruction ACKT 1 Used to gener...

Page 387: ...ng edge of SCL automatically output when ACKE 1 However not automatically cleared to 0 after acknowledge signal output Used in reception with 9 clock wait mode selected R ACKD Acknowledge Detection Clear Conditions ACKD 0 Set Conditions ACKD 1 Upon execution of a transfer start instruction in the I2 C When acknowledge signal is detected at the rising mode edge of SCL clock after completion of tran...

Page 388: ...e input 1 1 Used in the I2 C bus mode 9 clock wait Generates interrupt service request at rising edge of 9th SCL clock cycle In the case of master device makes SCL output low to enter wait state after output In the case of slave device makes SCL output low to request waits pulses are input R W WREL Wait State Cancellation Control 0 Wait state has been cancelled 1 Cancels wait state Automatically c...

Page 389: ...on termination of serial interface channel 0 transfer 1 CSIIF0 is set to 1 upon stop condition detection in I2 C bus mode R CLD SCK0 SCL P27 Pin LevelNote 2 0 Low level 1 High level Notes 1 When using the wake up function in the I2C mode be sure to set SIC to 1 2 When CSIE0 0 CLD is 0 Remark SVA Slave address register CSIIF0 Interrupt request flag supports the INTCSI0 CSIE0 Bit 7 of the serial ope...

Page 390: ...rial communication SCL output of various signals write instruction set Note 3 synchronization signal Address Master 7 bit data synchronized with to SIO0 when Indicates address value A6 to A0 SCL immediately after start CSIE0 1 for specification of slave condition signal instruction of on serial bus Transfer Master 1 bit data output in synchro serial transfer Indicates whether data direction nizati...

Page 391: ... data bus require the external pull up resistors to be output by N ch open drain Figure 16 44 Pin Configuration Caution Because the N ch open drain output must be set to high impedance at the time of data reception write FFH to the serial I O shift register 0 SIO0 in advance However when wake up function is used that is bit 5 WUP of serial operating mode register 0 CSIM0 is set do not write FFH to...

Page 392: ...0 SDA1 status during transmission is also taken into the serial I O shift register 0 SIO0 of the transmitting device a Comparison of SIO0 data before and after transmission In this case a transmission error is judged to have occurred if the two data values are different b Using the slave address register SVA Transmit data is set in SIO0 and SVA before transmission is performed After transmission t...

Page 393: ...tart Condition to Address Master device operation Transfer line Slave device operation Write SIO0 COI ACKD CMDD RELD CLD P27 WUP ACKE CMDT RELT CLC WREL SIC INTCSI0 SCL SDA0 SDA1 SIO0 Address SIO0 Address L H L L L L L 2 A6 1 3 4 5 6 7 8 9 1 2 3 4 5 A5 A4 A3 A2 A1 A0 W ACK D4 D5 D6 D7 Write SIO0 COI ACKD CMDD RELD CLD P27 WUP ACKE CMDT RELT CLC WREL SIC INTCSI0 SIO0 FFH L H L L L L L ...

Page 394: ...ta Master device operation Transfer line Slave device operation Write SIO0 COI ACKD CMDD RELD CLD P27 WUP ACKE CMDT RELT CLC WREL SIC INTCSI0 SCL SDA0 SDA1 SIO0 Data SIO0 Data L H L L L L L 2 D7 1 3 4 5 6 7 8 9 1 2 3 4 5 D6 D5 D4 D3 D2 D1 ACK D4 D5 D6 D7 Write SIO0 COI ACKD CMDD RELD CLD P27 WUP ACKE CMDT RELT CLC WREL SIC INTCSI0 L H L L L L L L L L D0 6 7 8 D3 D2 D1 SIO0 FFH SIO0 FFH ...

Page 395: ...ons described in 16 4 7 2 Avoidance Refer to 16 4 7 2 Limitation when used as the slave device in the I2C bus mode for details Master device operation Transfer line Slave device operationNote Write SIO0 COI ACKD CMDD RELD CLD P27 WUP ACKE CMDT RELT CLC WREL SIC INTCSI0 SCL SDA0 SDA1 SIO0 Address SIO0 Address H L L L L 2 D6 1 3 4 5 6 7 8 9 1 2 3 4 D5 D4 D3 D2 D1 D0 ACK A4 A5 A6 Write SIO0 COI ACKD ...

Page 396: ... a Start Condition to Address Master device operation Transfer line Slave device operation Write SIO0 COI ACKD CMDD RELD CLD P27 WUP ACKE CMDT RELT CLC WREL SIC INTCSI0 SCL SDA0 SDA1 SIO0 Address SIO0 FFH L H L L L L 2 A6 1 3 4 5 6 7 8 9 1 2 3 4 5 A5 A4 A3 A2 A1 A0 ACK D4 D5 D6 D7 Write SIO0 COI ACKD CMDD RELD CLD P27 WUP ACKE CMDT RELT CLC WREL SIC INTCSI0 L L L L L L R SIO0 Data ...

Page 397: ...ta Master device operation Transfer line Write SIO0 COI ACKD CMDD RELD CLD P27 WUP ACKE CMDT RELT CLC WREL SIC INTCSI0 SCL SDA0 SDA1 SIO0 FFH SIO0 FFH L H L H L L L 2 D7 1 3 4 5 6 7 8 9 1 2 3 4 5 D6 D5 D4 D3 D2 D1 ACK D4 D5 D6 D7 Write SIO0 COI ACKD CMDD RELD CLD P27 WUP ACKE CMDT RELT CLC WREL SIC INTCSI0 L L L L L L L L L L D0 6 7 8 D3 D2 D1 Slave device operation SIO0 Data SIO0 Data ...

Page 398: ...ock Wait 3 3 c Stop Condition Master device operation Transfer line Write SIO0 COI ACKD CMDD RELD CLD P27 WUP ACKE CMDT RELT CLC WREL SIC INTCSI0 SCL SDA0 SDA1 SIO0 FFH SIO0 Address H L L L 2 D6 1 3 4 5 6 7 8 9 1 2 3 4 D5 D4 D3 D2 D1 D0 NAK A4 A5 A6 Write SIO0 COI ACKD CMDD RELD CLD P27 WUP ACKE CMDT RELT CLC WREL SIC INTCSI0 L L L L D7 SIO0 Data Slave device operation ...

Page 399: ...tion 2 Because the N ch open drain output must be set to high impedance at the time of data reception write FFH to the serial I O shift register 0 SIO0 in advance However when wake up function is used that is bit 5 WUP of serial operating mode register 0 CSIM0 is set do not write FFH to SIO0 before data reception Without writing FFH to SIO0 the N ch open drain output is always high impedance state...

Page 400: ...t a start condition signal Set 1 in bit 3 CLC of the interrupt timing specification register SINT to drive the SCL pin high After setting CLC clear CLC to 0 and return the SCL pin to low If CLC remains 1 no serial clock is output If it is the master device which outputs the start condition and stop condition signals confirm that CLD is set to 1 after setting CLC to 1 This is because a slave device...

Page 401: ... program At this time control the low level width a in Figure 16 48 of the first serial clock at the timing used for setting the P27 output latch to 1 after execution of an SIO0 write instruction In addition if the acknowledge signal from the master is not output if data transmission from the slave is completed set 1 in the WREL flag of SINT and release the wait For these timings see Figure 16 46 ...

Page 402: ...ause if SCL line is being high impedance state during execution of write instruction to the SIO0 until next instruction execution SIO0 does not start the operation Therefore receive the data by manipulating the P27 output latch using program as shown in the Figure 16 49 For these timings see Figure 16 45 Figure 16 49 Slave Wait Release Reception Software operation Serial transmission Writing FFH t...

Page 403: ... wake up function 16 4 7 Restrictions on use of I2C bus mode The µPD78014Y subseries devices have the following restrictions 1 Restriction on master device operation in the I2C bus mode Applied device µPD78P014Y IE 78014 R EM Description When the master device outputs the serial clock via the SCL pin if the SCL rise time takes more than 1 32 of serial clock period then the master device sometimes ...

Page 404: ...riting FFH into SIO0 of the µPD78014Y Subseries device if the master device drives the SCL line to high level to output the start condition or stop condition signals then SIO0 shift operation is carried out in the µPD78014Y Subseries device slave device As a result written FFH is shifted and LSB of SIO0 becomes equal to the level of SDA0 SDA1 If the master device drives SCL to high level after dri...

Page 405: ...al operating mode register 0 CSIM0 and serial I O shift register 0 SIO0 of the slave device to 1 and FFH respectively before a stop condition signal is output Then the wake up function is enabled for the next slave address field which is sent from the master device and the N ch open drain output is high impedance state automatically As a result there is no influence on slave reception data Transfe...

Page 406: ...BIC The SCK0 SCL P27 pin output should be manipulated as described below 1 In the 3 wire serial I O mode and the 2 wire serial I O mode Output level of SCK0 SCL P27 pin is manipulated by the P27 output latch 1 Set serial operating mode register 0 CSIM0 SCK0 pin is set in the output mode and serial operation is enabled While serial transfer is suspended SCK0 is set to 1 2 Manipulate the content of ...

Page 407: ...NT by executing the bit manipulation instruction Figure 16 51 SCK0 SCL P27 Pin Configuration Remarks 1 This figure shows the relationship between each signal and does not show the internal circuit 2 CLC Bit 3 of the interrupt timing specification register SINT Note Level of SCL signal is determined by the following logic in the Figure 16 52 Figure 16 52 SCL Signal Logic SCK0 SCL P27 To internal ci...

Page 408: ...www DataSheet4U com CHAPTER 16 SERIAL INTERFACE CHANNEL 0 µPD78014Y Subseries 408 MEMO ...

Page 409: ...o the data transfer processing time is fast The start bit of 8 bit data to undergo serial transfer is switchable between MSB and LSB so it is possible to connect to devices of any start bit 3 wire serial I O mode is valid for connection of peripheral I O units and display controllers which incorporate a conventional synchronous clock serial interface as is the case with the 75X XL 78K and 17K Seri...

Page 410: ...uration Item Configuration Register Serial I O shift register 1 SIO1 Automatic data transmit receive address pointer ADTP Control register Timer clock select register 3 TCL3 Serial operating mode register 1 CSIM1 Automatic data transmit receive control register ADTC Port mode register 2 PM2 Note Note Refer to Figures 6 6 and 6 8 P20 P21 P23 to P26 Block Diagrams and Figures 6 7 and 6 9 P22 and P27...

Page 411: ...K1 P22 PM22 DIR DIR Internal Bus Serial I O Shift Register 1 SIO1 Hand shake P22 Output Latch Q R S Clear ARLD Serial Clock Counter SIO1 Write Internal Bus Timer Clock Select Register 3 TCL37 TCL36 TCL35 TCL34 4 Selector Selector TO2 fX 22 to fX 29 INTCSI1 Selector Serial Operating Mode Register 1 CSIE1 DIR ATE CSIM11CSIM10 TRF Automatic Data Transmit Receive Control Register RE ARLD ERCE ERR TRF ...

Page 412: ...IO1 RESET input makes SIO1 undefined Caution Do not write data to SIO1 while the automatic transmit receive function is activated 2 Automatic data transmit receive address pointer ADTP This register stores the value of the number of transmit data bytes 1 while the automatic transmit receive function is activated It is decremented automatically with data transmission reception ADTP is set with an 8...

Page 413: ...ister 3 TCL3 Serial operating mode register 1 CSIM1 Automatic data transmit receive control register ADTC 1 Timer clock select register 3 TCL3 This register sets the serial clock of serial interface channel 1 TCL3 is set with an 8 bit memory manipulation instruction RESET input sets TCL3 to 88H Remark Besides setting the serial clock of serial interface channel 1 TCL3 sets the serial clock of seri...

Page 414: ...lation frequency 2 Values in parentheses apply to operation with fX 10 0 MHz TCL33 TCL32 TCL31 TCL30 Serial Interface Channel 0 Serial Clock Selection 0 1 1 0 fX 22 Note 0 1 1 1 fX 23 1 25 MHz 1 0 0 0 fX 24 625 kHz 1 0 0 1 fX 25 313 kHz 1 0 1 0 fX 26 156 kHz 1 0 1 1 fX 27 78 1 kHz 1 1 0 0 fX 28 39 1 kHz 1 1 0 1 fX 29 19 5 kHz Other than above Setting prohibited TCL37 TCL36 TCL35 TCL34 Serial Inter...

Page 415: ...al I O mode 1 3 wire serial I O mode with automatic transmit receive function DIR Start Bit SI1 Pin Function SO1 Pin Function 0 MSB SI1 P20 Input SO1 CMOS output 1 LSB CSIE CSIM PM20 P20 PM21 P21 PM22 P22 Shift Register Serial Clock Counter SI1 P20 SO1 P21 SCK1 P22 1 11 1 Operation Operation Pin Function Pin Function Pin Function Control Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Operation stop Cle...

Page 416: ... This register sets automatic receive enable disable the operating mode strobe output enable disable busy input enable disable error check enable disable and displays automatic transmit receive execution and error detection ADTC is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets ADTC to 00H ...

Page 417: ...robe output disable 1 Strobe output enable R TRF Status of Automatic Transmit Receive FunctionNote 2 0 Detection of termination of automatic transmission reception This bit is set to 0 upon suspension of automatic transmission reception or when ARLD 0 1 During automatic transmission reception This bit is set to 1 when data is written to SIO1 R ERR Error Detection of Automatic Transmit Receive Func...

Page 418: ...th the serial operating mode register 1 CSIM1 CSIM1 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIM1 to 00H Symbol 7 6 5 4 3 2 1 0 Address When Reset R W CSIM1 CSIE1 DIR ATE 0 0 0 CSIM11 CSIM12 FF68H 00H R W CSIE CSIM PM20 P20 PM21 P21 PM22 P22 Shift Register Serial Clock Counter SI1 P20 SO1 P21 SCK1 P22 1 11 1 Operation Operation Pin Function Pin Function Pin Fu...

Page 419: ...o 0 0 2 Can be used freely as port function 3 Can be used as P20 CMOS input output when only transmitter is used Set bit 7 RE of ADTC to 0 Remark don t care PMxx Port mode register Pxx Output latch of port CSIM11 CSIM10 Serial Interface Channel 1 Clock Selection 0 x Clock externally input to SCK1 pinNote 1 1 0 8 bit timer register 2 TM2 output 1 1 Clock specified with bits 4 to 7 of timer clock se...

Page 420: ... clock SCK1 The transmit data is held in the SO1 latch and is output from the SO1 pin The receive data input to the SI1 pin is latched into SIO1 at the rising edge of SCK1 Upon termination of 8 bit transfer the SIO1 operation stops automatically and the interrupt request flag CSIIF1 is set Figure 17 5 3 Wire Serial I O Mode Timings Caution SO1 pin will be low by writing to SIO1 SCK1 SI1 SO1 CSIIF1...

Page 421: ...a write to SIO1 The SIO1 shift order remains unchanged Thus switch the MSB LSB start bit before writing data to the shift register 4 Start of transfer A serial transfer is started by setting transfer data in the serial I O shift register 1 SIO1 if the following two conditions have been satisfied The serial interface channel 1 operation control bit CSIE1 1 After an 8 bit serial transfer the interna...

Page 422: ...stored in the RAM by the set number of bytes Handshake signals STB and BUSY are supported by hardware to transmit receive data continuously OSD On Screen Display LSI and peripheral LSI including LCD controller driver can be connected without difficulty 1 Register setting The 3 wire serial I O mode with automatic transmit receive function is set with the serial operating mode register 1 CSIM1 and t...

Page 423: ...20 SO1 P21 SCK1 P22 1 11 1 Operation Operation Pin Function Pin Function Pin Function Control Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Operation stop Clear P20 P21 P22 0 CMOS CMOS CMOS input output input output input output 0 Note 3 Note 3 1 Operation Count SI1Note 3 SO1 SCK1 1 1 0 0 enable operation Input CMOS output Input 1 0 1 SCK1 CMOS output Notes 1 If the external clock input has been selec...

Page 424: ...rror in automatic transmission reception This bit is set to 0 when data is written to SIO1 1 Error occurred in automatic transmission reception R W ERCE Error Check Control of Automatic Transmit Receive Function 0 Error check disable in automatic transmission reception 1 Error check enable only when BUSY1 1 R W ARLD Operating Mode Selection of Automatic Transmit Receive Function 0 Single operating...

Page 425: ...egister ADTC to 1 3 Write any value to the serial I O shift register 1 SIO1 transfer start trigger Caution Writing any value to SIO1 orders the start of automatic transmit receive operation and the written value has no meaning The following operations are automatically carried out when a and b are carried out After the buffer RAM data specified with ADTP is transferred to SIO1 transmission is star...

Page 426: ...normal input output ports Figure 17 7 shows the basic transmit receive mode operation timings and Figure 17 8 shows the operation flowchart In addition Figure 17 9 shows the buffer RAM operation in 6 byte transmission reception Figure 17 7 Basic Transmit Receive Mode Operation Timings Cautions 1 Because in the basic transmit receive mode the automatic transmit receive function writes reads data to...

Page 427: ...e control register ADTC Start Write transmit data in buffer RAM Set ADTP to the value pointer value obtained by subtracting 1 from the number of transmit data bytes Write any data to SIO1 start trigger Write transmit data from buffer RAM to SIO1 Write receive data from SIO1 to buffer RAM Pointer value 0 TRF 0 End Decrement pointer value Yes No No Yes Software Execution Software Execution Hardware ...

Page 428: ...te transmission reception point Refer to Figure 17 9 b Transmission reception of the third byte is completed and transmit data 4 T4 is transferred from the buffer RAM to SIO1 When transmission of the fourth byte is completed the receive data 4 R4 is transferred from SIO1 to the buffer RAM and ADTP is decremented iii Completion of transmission reception Refer to Figure 17 9 c When transmission of t...

Page 429: ...smission reception point c Completion of transmission reception Receive data 1 R1 Receive data 2 R2 Receive data 3 R3 Transmit data 4 R4 Transmit data 5 R5 Transmit data 6 R6 FADFH FAC0H FAC5H Receive data 4 R4 2 0 SIO1 ADTP CSIIF1 1 Receive data 1 R1 Receive data 2 R2 Receive data 3 R3 Receive data 4 R4 Receive data 5 R5 Receive data 6 R6 FADFH FAC0H FAC5H 0 1 SIO1 ADTP CSIIF1 ...

Page 430: ... can be used as normal input output ports Figure 17 10 shows the basic transmission mode operation timings and Figure 17 11 shows the operation flowchart In addition Figure 17 12 shows the buffer RAM operation in 6 byte transmission Figure 17 10 Basic Transmit Mode Operation Timings Cautions 1 Because in the basic transmit mode the automatic transmit receive function reads data from the buffer RAM...

Page 431: ...ic data transmit receive control register ADTC Start Write transmit data in buffer RAM Set ADTP to the value pointer value obtained by subtracting 1 from the number of transmit data bytes Write any data to SIO1 Start trigger Write transmit data from buffer RAM to SIO1 Transmission operation Pointer value 0 TRF 0 End Decrement pointer value Yes No No Yes Software Execution Software Execution Hardwa...

Page 432: ...2 T2 is transferred from the buffer RAM to SIO1 ii 4th byte transmission point Refer to Figure 17 12 b Transmission of the third byte is completed and transmit data 4 T4 is transferred from the buffer RAM to SIO1 When transmission of the fourth byte is completed ADTP is decremented iii Completion of transmission Refer to Figure 17 12 c When transmission of the sixth byte is completed the interrupt...

Page 433: ...e transmission point c Completion of transmission Transmit data 1 T1 Transmit data 2 T2 Transmit data 3 T3 Transmit data 4 T4 Transmit data 5 T5 Transmit data 6 T6 FADFH FAC0H FAC5H 2 0 SIO1 ADTP CSIIF1 1 Transmit data 1 T1 Transmit data 2 T2 Transmit data 3 T3 Transmit data 4 T4 Transmit data 5 T5 Transmit data 6 T6 FADFH FAC0H FAC5H 0 1 SIO1 ADTP CSIIF1 ...

Page 434: ...usy control and strobe control are not performed the P20 SI1 P23 STB and P24 BUSY pins can be used as normal input output ports The repeat transmission mode operation timing is shown in Figure 17 13 and the operation flowchart in Figure 17 14 In addition buffer RAM operation in 6 byte transmission in the repeat transmit mode is shown in Figure 17 15 Figure 17 13 Repeat Transmit Mode Operation Timi...

Page 435: ...erial I O shift register 1 Start Write transmit data in buffer RAM Set ADTP to the value pointer value obtained by subtracting 1 from the number of transmit data bytes Write any data to SIO1 Start trigger Write transmit data from buffer RAM to SIO1 Transmission operation Pointer value 0 Decrement pointer value Yes No Software Execution Hardware Execution Reset ADTP ...

Page 436: ...AM to SIO1 ii Upon completion of transmission of 6 bytes Refer to Figure 17 15 b When transmission of the sixth byte is completed the interrupt request flag CSIIF1 is not set The ADTP is set with the initial pointer value again iii 7th byte transmission point Refer to Figure 17 15 c Transmit data 1 T1 is transferred from the buffer RAM to SIO1 again When transmission of the first byte is completed...

Page 437: ... of transmission of 6 bytes c 7th byte transmission point Transmit data 1 T1 Transmit data 2 T2 Transmit data 3 T3 Transmit data 4 T4 Transmit data 5 T5 Transmit data 6 T6 FADFH FAC0H FAC5H 0 0 SIO1 ADTP CSIIF1 Transmit data 1 T1 Transmit data 2 T2 Transmit data 3 T3 Transmit data 4 T4 Transmit data 5 T5 Transmit data 6 T6 FADFH FAC0H FAC5H 5 0 SIO1 ADTP CSIIF1 1 ...

Page 438: ...ansmission reception can be restarted and the remaining data can be transferred by setting CSIE1 to 1 and writing any data to the serial I O shift register 1 SIO1 Cautions 1 If the HALT instruction is executed during automatic transmission reception transfer is suspended and the HALT mode is set even during 8 bit data transfer When the HALT mode is cleared automatic transmission reception is resta...

Page 439: ...the slave device to the BUSY P24 pin The master device samples the input busy signal in synchronization with the falling of the serial clock Even if the busy signal becomes active while 8 bit data is being transmitted or received transmission reception by the master is not kept waiting If the busy signal is active at the rising edge of the serial clock 2 clocks after completion of transmission rec...

Page 440: ...signal was sampled To accurately release waiting the slave must keep the busy signal inactive at least for the duration of 1 5 clock Figure 17 19 shows the timing of the busy signal and releasing the waiting This figure shows an example where the busy signal is active as soon as transmission reception has been started Figure 17 19 Busy Signal and Wait Release when BUSY0 0 Figure 17 18 Operation Ti...

Page 441: ...tisfied Bit 5 ATE of the serial operation mode register 1 CSIM1 is set to 1 Bit 2 STRB of the automatic data transmission reception control register ADTC is set to 1 Usually the busy control and strobe control options are simultaneously used as handshake signals In this case the strobe signal is output from the STB P23 pin and the BUSY P24 pin is sampled and transmission reception can be kept wait...

Page 442: ...in 2 clocks The master samples the busy signal in synchronization of the falling of the leading side of the serial clock If a bit shift does not occur all the eight serial clocks that have been sampled are inactive If the sampled serial clocks are active it is assumed that a bit shift has occurred and error processing is executed by setting bit 4 ERR of the automatic transmission reception control...

Page 443: ... performed by an internal clock since the read write operations from to the buffer RAM are done in parallel with CPU processing the interval depends on the CPU processing at the moment of serial clock s eighth rising edge timing When the automatic data transmit receive function is performed by an external clock it must be chosen so that the interval may be longer than the value shown in b Figure 1...

Page 444: ...rnal clock performs In this case the interval is determined as follows by CPU processing Table 17 2 Interval by CPU Processing in Internal Clock Operation TSCK 1 fSCK fSCK Serial clock frequency TCPU 1 fCPU fCPU CPU clock set by bit 0 to bit 2 PCC0 to PCC2 of processor clock control register MAX a b a or b whichever greater Figure 17 23 Operating Timing in Operating Automatic Transmission Receptio...

Page 445: ...smit receive function is performed by an external clock When bit 1 CSIM11 of the serial operation mode register 1 CSIM1 is cleared to 0 the external clock performs When the automatic data transmit receive function is performed by an external clock it must be chosen so that the interval may be longer than the value shown below Table 17 3 Interval by CPU Processing in External Clock Operation TCPU 1...

Page 446: ...www DataSheet4U com CHAPTER 17 SERIAL INTERFACE CHANNEL 1 446 MEMO ...

Page 447: ... interrupt priority group and a low interrupt priority group by setting the priority specify flag register PR0L PR0H Multiple high priority interrupts can be applied to low priority interrupts If two or more interrupts with the same priority are simultaneously generated each interrupt has a predetermined priority see Table 18 1 A standby release signal is generated The maskable interrupt has four ...

Page 448: ...CSI0 End of serial interface channel 0 transfer Internal 000EH B 6 INTCSI1 End of serial interface channel 1 transfer 0010H 7 INTTM3 Reference time interval signal from watch 0012H timer 8 INTTM0 16 bit timer event counter match signal 0014H generation 9 INTTM1 8 bit timer event counter 1 match signal 0016H generation 10 INTTM2 8 bit timer event counter 2 match signal 0018H generation 11 INTAD End...

Page 449: ...errupt Request Priority Control Circuit Vector Table Address Generator Standby Release Signal Internal Bus MK IE PR ISP IF Interrupt Request Priority Control Circuit Vector Table Address Generator Standby Release Signal Internal Bus Sampling Clock Select Register SCS External Interrupt Mode Register INTM0 MK IE PR ISP IF Interrupt Request Priority Control Circuit Vector Table Address Generator Sta...

Page 450: ...t IF Interrupt request flag IE Interrupt enabled flag ISP Inservice priority flag MK Interrupt mask flag PR Priority specify flag Internal Bus MK IE PR ISP IF Interrupt Request Priority Control Circuit Vector Table Address Generator Standby Release Signal External Interrupt Mode Register INTM0 Edge Detector Internal Bus Interrupt Request Priority Control Circuit Vector Table Address Generator ...

Page 451: ...ves a listing of interrupt request flags interrupt mask flags and priority specify flag names corresponding to interrupt request sources Table 18 2 Various Flags Corresponding to Interrupt Request Sources Interrupt Source Interrupt Request Flag Interrupt Mask Flag Priority Specify Flag Register Register Register INTWDT TMIF4 IF0L TMMK4 MK0L TMPR4 PR0L INTP0 PIF0 PMK0 PPR0 INTP1 PIF1 PMK1 PPR1 INTP...

Page 452: ...ith a 16 bit memory manipulation instruction RESET input sets these registers to 00H Figure 18 2 Interrupt Request Flag Register Format Symbol 7 6 5 4 3 2 1 0 Address When Reset R W IF0L TMIF3 CSIIF1 CSIIF0 PIF3 PIF2 PIF1 PIF0 TMIF4 FFE0H 00H R W 7 6 5 4 3 2 1 0 IF0H 0 0 WTIFNote 0 ADIF TMIF2 TMIF1 TMIF0 FFE1H 00H R W IF Interrupt Request Flag 0 No interrupt request signal is generated 1 Interrupt...

Page 453: ... PMK3 PMK2 PMK1 PMK0 TMMK4 FFE4H FFH R W 7 6 5 4 3 2 1 0 MK0H 1 1 WTMKNote 1 ADMK TMMK2 TMMK1 TMMK0 FFE5H FFH R W MK Interrupt Servicing Standby Mode Control 0 Interrupt servicing standby mode clear enabled 1 Interrupt servicing standby mode clear disabled Note WTMK flag controls standby mode clear enabled disabled The interrupt function does not control Cautions 1 If TMMK4 flag is read when a wat...

Page 454: ...ster PR0 they are set with a 16 bit memory manipulation instruction RESET input sets these registers to FFH Figure 18 4 Priority Specify Flag Register Format Symbol 7 6 5 4 3 2 1 0 Address When Reset R W PR0L TMPR3 CSIPR1 CSIPR0 PPR3 PPR2 PPR1 PPR0 TMPR4 FFE8H FFH R W 7 6 5 4 3 2 1 0 PR0H 1 1 1 1 ADPR TMPR2 TMPR1 TMPR0 FFE9H FFH R W PR Priority Level Selection 0 High priority level 1 Low priority ...

Page 455: ...ess When Reset R W INTM0 ES31 ES30 ES21 ES20 ES11 ES10 0 0 FFECH 00H R W ES11 ES10 INTP0 Valid Edge Selection 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both falling and rising edges ES21 ES20 INTP1 Valid Edge Selection 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both falling and rising edges ES31 ES30 INTP2 Valid Edge Selection 0 0 Falling edge 0 1 Rising edge 1 0...

Page 456: ... 18 6 Sampling Clock Select Register Format Symbol 7 6 5 4 3 2 1 0 Address When Reset R W SCS 0 0 0 0 0 0 SCS1 SCS0 FF47H 00H R W SCS1 SCS0 INTP0 Sampling Clock Selection 0 0 fX 2N 1 0 1 Setting prohibited 1 0 fX 26 156 kHz 1 1 fX 27 78 1 kHz Caution fX 2N 1 is a clock to be supplied to the CPU and fX 26 and fX 27 are clocks to be supplied to the peripheral hardware fX 2N 1 stops in the HALT mode ...

Page 457: ...is detected a When input is less than the sampling cycle tSMP b When input is equal to or twice the sampling cycle tSMP c When input is twice or more than the sampling cycle tSMP tSMP INTP0 PIF0 Sampling Clock L Because INTP0 level is not high level in sampling PIF0 output remains at low level Sampling Clock INTP0 PIF0 1 2 Because sampling INTP0 level is high level twice in succession in 2 PIF0 fl...

Page 458: ...nto a stack and the IE flag is reset to 0 If a maskable interrupt request is acknowledged the contents of the priority specify flag of the acknowledged interrupt are transferred to the ISP flag The contents of acknowledged interrupt is also saved into the stack with the PUSH PSW instruction It is reset from the stack with the RETI RETB and POP PSW instructions RESET input sets PSW to 02H Figure 18...

Page 459: ... into PC and branched A new non maskable interrupt request generated during execution of a non maskable interrupt servicing program is acknowledged after the current execution of the non maskable interrupt servicing program is terminated following RETI instruction execution and one main routine instruction is executed If a new non maskable interrupt request is generated twice or more during non ma...

Page 460: ...lag Start WDTM4 1 with watchdog timer mode selected Overflow in WDT WDTM3 0 with non maskable interrupt request selected Interrupt request generation WDT interrupt servicing Interrupt control register unaccessed Interrupt service start No Yes No Yes No Yes No Yes No Yes Interval timer Reset processing Interrupt request reserve CPU Processing Instruction Instruction PSW PC save jump to interrupt se...

Page 461: ...non maskable interrupt servicing program execution NMI request 2 NMI request 1 Execution of one instruction Main Routine NMI request 1 executed NMI request 2 kept pending Pending NMI request 2 is serviced NMI request 3 NMI request 2 NMI request 1 Execution of one instruction Main Routine NMI request 1 executed NMI request 2 kept pending NMI request 3 kept pending Pending NMI request 2 is serviced ...

Page 462: ... Remark 1 clock 1 fCPU fCPU CPU clock If two or more maskable interrupt requests are generated simultaneously the request specified for higher priority with the priority specify flag is acknowledged first If two or more requests are specified for the same priority with the priority specify flag the interrupt request with the higher default priority is acknowledged first Any reserved interrupt requ...

Page 463: ...an Interrupt with low priority is being serviced Start IF 1 MK 0 PR 0 Any simul taneously generated PR 0 interrupt requests Any simul taneously generated high priority interrupt requests IE 1 ISP 1 Interrupt request reserve Interrupt request reserve Interrupt request reserve Any high priority interrupt among simultaneously generated PR 0 interrupt requests IE 1 Vectored interrupt servicing Yes No ...

Page 464: ...equest Acknowledge Timing Maximum Time Remark 1 clock 1 fCPU fCPU CPU clock CPU Processing IF PR 1 IF PR 0 Instruction Instruction PSW PC Save Jump to Interrupt Servicing Interrupt Servicing Program 12 Clocks 15 Clocks 13 Clocks CPU Processing IF PR 1 IF PR 0 Instruction Divide Instruction 50 Clocks 12 Clocks 63 Clocks 65 Clocks PSW PC Save Jump to Interrupt Servicing Interrupt Servicing Program ...

Page 465: ...upt nesting is controlled by using the programmable priority If an interrupt with the same level of priority as or the higher priority than the interrupt currently serviced occurs that interrupt can be accepted and nested If an interrupt with a priority lower than that of the currently serviced interrupt occurs that interrupt cannot be accepted and nested An interrupt that is not accepted and nest...

Page 466: ...PR 0 High priority level PR 1 Low priority level IE 0 Interrupt request acknowledge disabled During interrupt INTxx servicing two interrupt requests INTyy and INTzz are acknowledged and a multiple interrupt is generated An EI instruction is issued before each interrupt request acknowledge and the interrupt request acknowledge enable state is set Example 2 Multiple interrupt is not generated by pri...

Page 467: ...d in interrupt INTxx servicing an EI instruction is not issued interrupt request INTyy is not acknowledged and a multiple interrupt is not generated The INTyy request is reserved and acknowledged after 1 instruction execution of the main processing PR 0 High priority level IE 0 Interrupt request acknowledge disabled Main Processing INTxx Servicing INTyy Servicing EI INTxx PR 0 IE 0 INTyy PR 0 RETI...

Page 468: ... MK0L MK0H PR0L PR0H and INTM0 registers Caution BRK instruction is not an interrupt request reserve instruction described above However in a software interrupt started by the execution of BRK instruction the IE flag is cleared to 0 Therefore interrupt requests are not acknowledged even when a maskable interrupt request is issued during the execution of the BRK instruction However non maskable int...

Page 469: ...le 18 5 Basic configuration is shown in Figure 18 17 Table 18 5 Test Input Source Figure 18 17 Basic Configuration of Test Function IF Test Input Flag MK Test Mask Flag 18 5 1 Test function control registers The following three types of registers are used to control the test functions Interrupt request flag register 0H IF0H Interrupt mask flag register 0H MK0H Key return mode register KRM Test Inp...

Page 470: ... W IF0H 0 0 WTIF 0 ADIF TMIF2 TMIF1 TMIF0 FFE1H 00H R W WTIF Watch timer overflow detection flag 0 Non detection 1 Detection Caution Be sure to set bits 4 6 and 7 to 0 2 Interrupt mask flag register 0H MK0H This register sets standby mode clear enable disable by watch timer MK0H is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets MK0H to FFH Figure 18 19 Interrupt Mask Fl...

Page 471: ...ase signal is generated if it is not masked by the interrupt mask flag WTMK By checking the WTIF flag in a cycle shorter than the overflow cycle of the watch timer the watch function can be effected 2 External test input signal If a falling edge is input to a pin of port 4 P40 to P47 an external test input signal INTP4 is generated setting the KRIF flag At this time the standby release signal is g...

Page 472: ...www DataSheet4U com CHAPTER 18 INTERRUPT FUNCTIONS AND TEST FUNCTION 472 MEMO ...

Page 473: ...n AD0 to AD7 Multiplexed address data bus P40 to P47 A8 to A15 Address bus P50 to P57 RD Read strobe signal P64 WR Write strobe signal P65 WAIT Wait signal P66 ASTB Address strobe signal P67 Table 19 2 State of Port 4 to Port 6 Pins in External Memory Expansion Mode Port Port 4 Port 5 Port 6 External 0 to 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Expansion Mode Single chip mode Port Port Port 256 bytes ex...

Page 474: ...ansion mode when MM2 to MM0 100 256 bytes expansion mode when MM2 to MM0 011 Single chip mode SFR Internal High speed RAM Reserved Buffer RAM Reserved Full address mode when MM2 to MM0 111 16 Kbytes expansion mode when MM2 to MM0 101 4 Kbytes expansion mode when MM2 to MM0 100 256 bytes expansion mode when MM2 to MM0 011 Single chip mode FFFFH F F 0 0 H FEFFH FD00H FCFFH FAE0H FADFH FAC0H FABFH FA...

Page 475: ... 256 bytes expansion mode when MM2 to MM0 011 Single chip mode SFR Internal High speed RAM Reserved Buffer RAM Reserved Full address mode when MM2 to MM0 111 16 Kbytes expansion mode when MM2 to MM0 101 4 Kbytes expansion mode when MM2 to MM0 100 256 bytes expansion mode when MM2 to MM0 011 Single chip mode FFFFH F F 0 0 H FEFFH FB00H FAFFH FAE0H FADFH FAC0H FABFH FA80H FA7FH A 0 0 0 H 9FFFH 7 0 0...

Page 476: ...P67 Pins Condition Expansion Mode Selection P40 to P47 P50 to P53 P54 P55 P56 P57 P64 to P67 0 0 0 Single chip mode Port Input Port mode 0 0 1 mode Output 0 1 1 Memory 256 bytes AD0 to AD7 Port mode P64 RD expansion mode P65 WR 1 0 0 mode 4 Kbytes A8 to A11 Port mode P66 WAIT mode P67 ASTB 1 0 1 16 Kbytes A12 A13 Port mode mode 1 1 1 Full address A14 A15 modeNote Other than above Setting prohibite...

Page 477: ...ot output maintains high level 3 WAIT pin Alternate function P66 External wait signal input pin When the external wait function is not used the WAIT pin can be used as an input output port During internal memory access the external wait signal is ignored 4 ASTB pin Alternate function P67 Address strobe signal output pin Timing signal is always output regardless of the data access or instruction fe...

Page 478: ...b When with Wait PW1 PW0 0 1 Setup c When External Wait PW1 PW0 1 1 Setup ASTB RD AD0 to AD7 A8 to A15 Low order address Instruction code High order address ASTB RD AD0 to AD7 A8 to A15 Internal wait signal 1 clock wait Low order address Instruction code High order address ASTB RD AD0 to AD7 A8 to A15 WAIT Low order address Instruction code High order address ...

Page 479: ...etup b When with Wait PW1 PW0 0 1 Setup c When External Wait PW1 PW0 1 1 Setup ASTB RD AD0 to AD7 A8 to A15 Low order address Read data High order address ASTB RD AD0 to AD7 A8 to A15 Internal wait signal 1 clock wait Low order address Read data High order address ASTB RD AD0 to AD7 A8 to A15 WAIT Low order address Read data High order address ...

Page 480: ...en with Wait PW1 PW0 0 1 Setup c When External Wait PW1 PW0 1 1 Setup ASTB WR AD0 to AD7 A8 to A15 Hi Z Low order address Write data High order address ASTB WR AD0 to AD7 A8 to A15 Internal wait signal 1 clock wait Hi Z Low order address Write data High order address ASTB WR AD0 to AD7 A8 to A15 WAIT Hi Z Low order address Write data High order address ...

Page 481: ...h Wait PW1 PW0 0 1 Setup c When External Wait PW1 PW0 1 1 Setup ASTB RD AD0 to AD7 A8 to A15 WR Low order address Read data Write data High order address ASTB WR AD0 to AD7 A8 to A15 Internal wait signal 1 clock wait RD Low order address Read data Write data High order address ASTB AD0 to AD7 A8 to A15 WAIT WR RD Low order address Read data Write data High order address ...

Page 482: ... 7 Example of Memory Connection with µPD78014 Caution At the external memory read modify write timing the time from RD signal rising to write data output is very short so that the write data sometimes conflicts with the output data from external memory SRAM etc In this case it is possible to avoid data conflict by not using the following instructions which generate read modify write timing XCH A a...

Page 483: ...effective to hold data memory contents with ultra low current consumption Because this mode can be cleared upon interrupt request it enables intermittent operations to be carried out However because a wait time is necessary to secure an oscillation stabilization time after the STOP mode is cleared select the HALT mode if it is necessary to start processing immediately upon interrupt request In any...

Page 484: ...l the oscillation stabilizes is controlled with the oscillation stabilization time select register OSTS OSTS is set with an 8 bit memory manipulation instruction RESET input sets OSTS to 04H Therefore when the STOP mode is cleared with RESET input the time till it is cleared is 218 fX Figure 20 1 Oscillation Stabilization Time Select Register Format Symbol 7 6 5 4 3 2 1 0 Address When Reset R W OS...

Page 485: ... Operation enabled Operation stop 8 bit timer event counter Operation enabled Operation enabled when TI1 and TI2 are selected for the count clock Watchdog timer Operation enabled Operation stop A D converter Operation enabled Operation stop Watch timer Operation enabled Operation enabled Operation enabled when fX 28 is selected when fXT is selected for the count clock for the count clock Serial Ot...

Page 486: ...rrupt request which has cleared the standby status is acknowledged 2 Wait time will be as follows When branched to the vector 16 5 to 17 5 clocks When not branched to the vector 4 5 to 5 5 clocks b Clear upon non maskable interrupt request The HALT mode is cleared and vectored interrupt service is carried out when the non maskable interrupt request is generated whether interrupt request acknowledg...

Page 487: ...ice execution 1 HALT mode hold Non maskable interrupt request Interrupt service execution Test input 0 Next address instruction execution 1 HALT mode hold RESET input Reset processing Remark don t care d Clear upon RESET input The HALT mode is cleared when the RESET signal inputs As is the case with normal reset operation a program is executed after branch to the reset vector address Figure 20 3 H...

Page 488: ...nal A8 to A15 Status before STOP instruction execution is held Expansion ASTB Low level WR RD High level WAIT High impedance 20 2 2 STOP mode 1 STOP mode set and operating status The STOP mode is set by executing the STOP instruction It can be set only with the main system clock Cautions 1 When the STOP mode is set X1 input is internally short circuited to VSS ground potential to suppress the leak...

Page 489: ...next address instruction is executed Figure 20 4 STOP Mode Clear upon Interrupt Request Generation Remark The broken line indicates the case when the interrupt request which has cleared the standby status is acknowledged b Clear upon unmasked test input The STOP mode is cleared when the unmasked test signal inputs After the lapse of oscillation stabilization time the instruction at the next addres...

Page 490: ...upt service execution 0 1 0 1 Next address instruction execution 0 1 0 0 1 1 1 Interrupt service execution 1 STOP mode hold Test input 0 Next address instruction execution 1 STOP mode hold RESET input Reset processing Remark don t care Remarks 1 fX Main system clock oscillation frequency 2 Values in parentheses apply to operation with fX 10 0 MHz Table 20 4 Operation after STOP Mode Clear Operatin...

Page 491: ...stabilization time just after reset clear When a high level is input to the RESET pin the reset is cleared and program execution starts after the lapse of oscillation stabilization time 218 fX The reset applied by watchdog timer overflow is automatically cleared after a reset and program execution starts after the lapse of oscillation stabilization time 218 fX see Figures 21 2 to 21 4 Cautions 1 F...

Page 492: ... High Impedance Reset Period Oscillation Stop Oscillation Stabilization Time Wait X1 Watchdog Timer Overflow Internal Reset Signal Port Pin Normal Operation Normal Operation Reset Processing High Impedance Oscillation Stabilization Time Wait Reset Period Oscillation Stop X1 RESET Internal Reset Signal Port Pin Normal Operation Normal Operation Reset Processing Delay Delay High Impedance Stop Instr...

Page 493: ...t register OSTS 04H 16 bit timer event counter Timer register TM0 0000H Compare register CR00 Undefined Capture register CR01 Undefined Clock select register TCL0 00H Mode control register TMC0 00H Output control register TOC0 00H 8 bit timer event counter Timer registers TM1 TM2 00H Compare registers CR10 CR20 Undefined Clock select register TCL1 00H Mode control register TMC1 00H Output control ...

Page 494: ...ister SVA Undefined Automatic data transmit receive control register ADTC 00H Automatic data transmit receive address pointer ADTP 00H Interrupt timing specify register SINT 00H A D converter Mode register ADM 01H Conversion result register ADCR Undefined Input select register ADIS 00H Interrupt Request flag registers IF0L IF0H 00H Mask flag registers MK0L MK0H FFH Priority specify flag registers ...

Page 495: ...ences between µPD78P014 78P014Y and Mask ROM Version Note When RESET is input the internal PROM capacity is set to 32 Kbytes internal high speed RAM capacity to 1024 bytes Caution The noise resistance and noise radiation differs between PROM versions and mask ROM versions If considering replacing PROM versions with mask ROM versions during the process from trial manufacturing to mass production ev...

Page 496: ...ing prohibited RAM2 RAM1 RAM0 Internal High Speed RAM Capacity Selection 0 0 0 768 bytes 0 0 1 640 bytes 0 1 0 512 bytes 0 1 1 384 bytes 1 0 0 256 bytes 1 0 1 Setting prohibited 1 1 0 1024 bytes 1 1 1 896 bytes Note The value of the memory size switching register at reset depends on the model see Table 22 2 Table 22 2 Internal Memory Size Switching Register Value at Reset Part Number Value at Rese...

Page 497: ...V is applied to the VPP pin and a low level signal is applied to the RESET pin the µPD78P014 and 78P014Y are set to the PROM programming mode This is one of the operating modes shown in Table 22 3 below according to the setting of the CE and OE pins The PROM contents can be read by setting the read mode Table 22 3 PROM Programming Operating Modes Pin RESET VPP VDD CE OE D0 to D7 Operating mode Pro...

Page 498: ...pulse active low to the CE pin 6 Verify mode If written proceed to step 8 If not written repeat steps 4 through 6 If you repeat 25 times and it can t be written proceed to 7 7 Stop the write operation as a defective device 8 Supply write data and repeat times from 4 through 6 3 ms program pulse additional write 9 Increment the address 10 Repeat steps 4 through 9 to the last address The timing for ...

Page 499: ...10 7 Last Address Start Supply Power Voltage Supply Initial Address Supply Write Data Supply Program Pulse Verify Mode Additional Write 3Xms pulse Increment Address Last Address End of Write Defective device Write OK Write disabled Less than 25 times Write disabled 25th time X Write repeat times Last Address ...

Page 500: ...V to the VPP pin Unused pins are handled as shown in 1 5 or 2 5 Pin Configurations Top View 2 PROM programming mode 2 Supply 5 V to the VDD and VPP pins 3 Input address of data to be read to pins A0 to A16 4 Read mode 5 Output data to pins D0 to D7 The timing for steps 2 to 5 above is shown in Figure 22 to 4 Figure 22 4 PROM Read Timing A0 to A14 CE Input OE Input D0 to D7 Hi Z Address Input Data ...

Page 501: ...y lamp If a filter has been attached to the ultraviolet ray lamp remove the filter before erasing 22 4 Opaque Film on Erasure Window for µPD78P014DW 78P014YDW When erasing EPROM contents be sure to cover the erasure window with a shading film to prevent unintentional erasure of EPROM contents by light source other than the ultraviolet ray lamp and to prevent a light source from unintentionally aff...

Page 502: ...www DataSheet4U com CHAPTER 22 µPD78P014 78P014Y 502 MEMO ...

Page 503: ...R 23 INSTRUCTION SET The instruction sets for the µPD78014 and 78014Y Subseries are described in the following pages For the details of operations and mnemonics instruction codes of each instruction refer to the 78K 0 Series User s Manual Instructions U12326E ...

Page 504: ...her function names X A C etc or absolute names names in parentheses in the table below R0 R1 R2 etc can be used for description Table 23 1 Operand Identifiers and Description Methods Identifier Description Method r X R0 A R1 C R2 B R3 E R4 D R5 L R6 H R7 rp AX RP0 BC RP1 DE RP2 HL RP3 sfr Special function register symbolNote sfrp Special function register symbols 16 bit manipulatable register even...

Page 505: ...uxiliary carry flag Z Zero flag RBS Register bank select flag IE Interrupt request enable flag NMIS Non maskable interrupt servicing flag Memory contents indicated by address or register contents in parentheses XH XL Higher 8 bits and lower 8 bits of 16 bit register Logical product AND Logical sum OR Exclusive logical sum exclusive OR Inverted data addr16 16 bit immediate data or label jdisp8 Sign...

Page 506: ...2m DE A A HL 1 8 10 2n A HL HL A 1 8 10 2m HL A A HL byte 2 16 18 2n A HL byte HL byte A 2 16 18 2m HL byte A A HL B 1 12 14 2n A HL B HL B A 1 12 14 2m HL B A A HL C 1 12 14 2n A HL C HL C A 1 12 14 2m HL C A Notes 1 When the internal high speed RAM area is accessed or instruction with no data access 2 When an area except the internal high speed RAM area is accessed 3 Except r A Remarks 1 One ins...

Page 507: ... 2 12 16 saddrp AX AX sfrp 2 16 AX sfrp sfrp AX 2 16 sfrp AX AX rp Note 4 1 8 AX rp rp AX Note 4 1 8 rp AX AX addr16 3 20 24 4n AX addr16 addr16 AX 3 20 24 4m addr16 AX XCHW AX rp Note 4 1 8 AX rp Notes 1 When the internal high speed RAM area is accessed or instruction with no data access 2 When an area except the internal high speed RAM area is accessed 3 Except r A 4 Only when rp BC DE or HL Rem...

Page 508: ...e ration A r Note 3 2 8 A CY A r r A 2 8 r CY r A A saddr 2 8 10 A CY A saddr A addr16 3 16 18 2n A CY A addr16 A HL 1 8 10 2n A CY A HL A HL byte 2 16 18 2n A CY A HL byte A HL B 2 16 18 2n A CY A HL B A HL C 2 16 18 2n A CY A HL C ADDC A byte 2 8 A CY A byte CY saddr byte 3 12 16 saddr CY saddr byte CY A r Note 3 2 8 A CY A r CY r A 2 8 r CY r A CY A saddr 2 8 10 A CY A saddr CY A addr16 3 16 18...

Page 509: ...dr byte 3 12 16 saddr CY saddr byte CY ration A r Note 3 2 8 A CY A r CY r A 2 8 r CY r A CY A saddr 2 8 10 A CY A saddr CY A addr16 3 16 18 2n A CY A addr16 CY A HL 1 8 10 2n A CY A HL CY A HL byte 2 16 18 2n A CY A HL byte CY A HL B 2 16 18 2n A CY A HL B CY A HL C 2 16 18 2n A CY A HL C CY AND A byte 2 8 A A byte saddr byte 3 12 16 saddr saddr byte A r Note 3 2 8 A A r r A 2 8 r r A A saddr 2 8...

Page 510: ...ag tion Note 1 Note 2 Z AC CY Group 8 bit XOR A byte 2 8 A A byte Ope saddr byte 3 12 16 saddr saddr byte ration A r Note 3 2 8 A A r r A 2 8 r r A A saddr 2 8 10 A A saddr A addr16 3 16 18 2n A A addr16 A HL 1 8 10 2n A A HL A HL byte 2 16 18 2n A A HL byte A HL B 2 16 18 2n A A HL B A HL C 2 16 18 2n A A HL C CMP A byte 2 8 A byte saddr byte 3 12 16 saddr byte A r Note 3 2 8 A r r A 2 8 r A A sa...

Page 511: ... Accumulator after Subtract Bit MOV1 CY saddr bit 3 12 14 CY saddr bit Manipu CY sfr bit 3 14 CY sfr bit lation CY A bit 2 8 CY A bit CY PSW bit 3 14 CY PSW bit CY HL bit 2 12 14 2n CY HL bit saddr bit CY 3 12 16 saddr bit CY sfr bit CY 3 16 sfr bit CY A bit CY 2 8 A bit CY PSW bit CY 3 16 PSW bit CY HL bit CY 2 12 16 2n 2m HL bit CY Notes 1 When the internal high speed RAM area is accessed or ins...

Page 512: ...n CY CY HL bit SET1 saddr bit 2 8 12 saddr bit 1 sfr bit 3 16 sfr bit 1 A bit 2 8 A bit 1 PSW bit 2 12 PSW bit 1 HL bit 2 12 16 2n 2m HL bit 1 CLR1 saddr bit 2 8 12 saddr bit 0 sfr bit 3 16 sfr bit 0 A bit 2 8 A bit 0 PSW bit 2 12 PSW bit 0 HL bit 2 12 16 2n 2m HL bit 0 SET1 CY 1 4 CY 1 1 CLR1 CY 1 4 CY 0 0 NOT1 CY 1 4 CY CY Notes 1 When the internal high speed RAM area is accessed or instruction ...

Page 513: ...AC CY Group Call CALL addr16 3 14 SP 1 PC 3 H SP 2 PC 3 L Return PC addr16 SP SP 2 CALLF addr11 2 10 SP 1 PC 2 H SP 2 PC 2 L PC15 11 00001 PC10 0 addr11 SP SP 2 CALLT addr5 1 12 SP 1 PC 1 H SP 2 PC 1 L PCH 00000000 addr5 1 PCL 00000000 addr5 SP SP 2 BRK 1 12 SP 1 PSW SP 2 PC 1 H SP 3 PC 1 L PCH 003FH PCL 003EH SP SP 3 IE 0 RET 1 12 PCH SP 1 PCL SP SP SP 2 RETI 1 12 PCH SP 1 PCL SP R R R PSW SP 2 S...

Page 514: ...16 PC PC 3 jdisp8 if A bit 0 PSW bit addr16 4 22 PC PC 4 jdisp8 if PSW bit 0 HL bit addr16 3 20 22 2n PC PC 3 jdisp8 if HL bit 0 BTCLR saddr bit addr16 4 20 24 PC PC 4 jdisp8 if saddr bit 1 then reset saddr bit sfr bit addr16 4 24 PC PC 4 jdisp8 if sfr bit 1 then reset sfr bit A bit addr16 3 16 PC PC 3 jdisp8 if A bit 1 then reset A bit PSW bit addr16 4 24 PC PC 4 jdisp8 if PSW bit 1 then reset PS...

Page 515: ... saddr 0 CPU SEL RBn 2 8 RBS1 0 n Control NOP 1 4 No Operation EI 2 12 IE 1 Enable Interrupt DI 2 12 IE 0 Disable Interrupt HALT 2 12 Set HALT Mode STOP 2 12 Set STOP Mode Notes 1 When the internal high speed RAM area is accessed or instruction with no data access 2 When an area except the internal high speed RAM area is accessed Remarks 1 One instruction clock cycle is one cycle of the CPU clock ...

Page 516: ...Sheet4U com CHAPTER 23 INSTRUCTION SET 516 23 3 Instructions Listed by Addressing Type 1 8 bit instructions MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MULU DIVUW INC DEC ROR ROL RORC ROLC ROR4 ROL4 PUSH POP DBNZ ...

Page 517: ... ADD ADD ADD ADD ADD RORC SUBC ADDC ADDC ADDC ADDC ADDC ROLC AND SUB SUB SUB SUB SUB OR SUBC SUBC SUBC SUBC SUBC XOR AND AND AND AND AND CMP OR OR OR OR OR XOR XOR XOR XOR XOR CMP CMP CMP CMP CMP r MOV MOV INC ADD DEC ADDC SUB SUBC AND OR XOR CMP B C DBNZ sfr MOV MOV saddr MOV MOV DBNZ INC ADD DEC ADDC SUB SUBC AND OR XOR CMP addr16 MOV PSW MOV MOV PUSH POP DE MOV HL MOV ROR4 ROL4 HL byte MOV HL B...

Page 518: ...VW addr16 MOVW SP MOVW MOVW Note Only when rp BC DE HL 3 Bit manipulation instructions MOV1 AND1 OR1 XOR1 SET1 CLR1 NOT1 BT BF BTCLR Second Operand A bit sfr bit saddr bit PSW bit HL bit CY addr16 None First Operand A bit MOV1 BT SET1 BF CLR1 BTCLR sfr bit MOV1 BT SET1 BF CLR1 BTCLR saddr bit MOV1 BT SET1 BF CLR1 BTCLR PSW bit MOV1 BT SET1 BF CLR1 BTCLR HL bit MOV1 BT SET1 BF CLR1 BTCLR CY MOV1 MO...

Page 519: ...tions CALL CALLF CALLT BR BC BNC BZ BNZ BT BF BTCLR DBNZ Second Operand AX addr16 addr11 addr5 addr16 First Operand Basic instruction BR CALL CALLF CALLT BR BR BC BNC BZ BNZ Compound instruction BT BF BTCLR DBNZ 5 Other instructions ADJBA ADJBS BRK RET RETI RETB SEL NOP EI DI HALT STOP ...

Page 520: ...www DataSheet4U com CHAPTER 23 INSTRUCTION SET 520 MEMO ...

Page 521: ...1024 bytes µPD78015F 1024 bytes µPD78016F 1024 bytes µPD78018F 1024 bytes µPD78P018F 1024 bytes Internal expansion RAM size None µPD78011F None µPD78012F None µPD78013F None µPD78014F None µPD78015F 512 bytes µPD78016F 512 bytes µPD78018F 1024 bytes µPD78P018F 1024 bytes Operation mode of serial 3 wire 2 wire SBI I2 C 1 ch 3 wire 2 wire I2 C 1 ch interface Y Subseries 3 wire with automatic 3 wire ...

Page 522: ...usy signal from falling edge of SCK0 following acknowledge signal in SBI mode Automatic data transmission None Provided reception interval specification register ADTI Package 64 pin plastic shrink DIP 64 pin plastic shrink DIP 64 pin plastic shrink DIP 750 mil 750 mil 750 mil 64 pin ceramic shrink DIP 64 pin plastic QFP 64 pin ceramic shrink DIP w window 750 mil Note 14 14 mm w window 750 mil Note...

Page 523: ... B DEVELOPMENT TOOLS 523 APPENDIX B DEVELOPMENT TOOLS The following development tools are available for the development of systems which employ the µPD78014 and 78014Y Subseries Figure B 1 shows the development tools configuration ...

Page 524: ...er Host machine PC or EWS Language processing software Target system Embedded software Real time OS OS Fuzzy inference development support system In circuit emulator Emulation probe Emulation board Interface adapter Only for integrated debugger Conversion socket or Conversion adapter PROM programming environment PROM programmer Programmer adapter PROM version Interface adapter Only for integrated ...

Page 525: ...8K0 CC78K 0 This is a program to convert a program written in C language into an object code executable with C Compiler Package a microcontroller Use CC78K 0 C compiler package in combination with RA78K 0 assembler package and DF78014 device file option Part Number µS CC78K0 DF78014Note This file contains device specific information Device file Use DF78014 device file in combination with RA78K 0 C...

Page 526: ...Y and is connected PA 78P014GC to the PG 1500 PROM programmer adapter PA 78P014CW 64 pin plastic shrink DIP CW type PA 78P014GC 64 pin plastic QFP GC AB8 type Remark Part number changes by the host machine or OS to be used µS PG1500 Note MS DOS Ver 5 0 or later have a task swap function but this task swap function cannot be used in the above software PG 1500 Controller The PG 1500 is controlled fr...

Page 527: ... in circuit emulator for debugging hardware and or software when a system is In circuit emulator developed with 78K 0 Series devices This emulator is designed to be used with the For screen debugger screen debugger SD78K 0 This is used together with emulation probe This emulator provides an efficient debugging environment by connecting it with a host computer and a PROM programmer IE 78014 R EM Th...

Page 528: ...ality will thus be improved This is used together with the separately sold device file DF78014 Part Number µS SM78K0 B 3 2 Software 1 3 Remark Part number changes by the host machine or OS to be used µS SM78K0 Host Machine Operating System Supply Medium AA13 PC 9800 series MS DOS 3 5 inch 2HD Ver 3 30 to Ver 6 2Note Windows Ver 3 0 to Ver 3 1 AB13 IBM PC AT and compatible Refer to B 4 3 5 inch 2HC...

Page 529: ...orating function extension modules such as task debugger and system performance analyzer This is used together with the separately sold device file DF78014 Part Number µS ID78K0 Host Machine Operating System Supply Medium AA13 PC 9800 series MS DOS 3 5 inch 2HD Ver 3 30 to Ver 6 2Note Windows Ver 3 1 AB13 IBM PC AT and compatible See B 4 3 5 inch 2HC machine Japanese Windows BB13 IBM PC AT and com...

Page 530: ...sed together with the separately sold device file RA78K 0 CC78K 0 SM78K0 ID78K0 SD78K 0 Part Number µS DF78014 Host Machine Operating System Supply Medium 5A13 PC 9800 series MS DOS 3 5 inch 2HD 5A10 Ver 3 30 to 5 inch 2HD Ver 6 2Note 7B13 IBM PC AT and compatible Refer to B 4 3 5 inch 2HC 7B10 machine 5 inch 2HC Note DF78014 can be used in RA78K 0 CC78K 0 SM78K0 and SD78K 0 all in common Remark P...

Page 531: ...5 0 VNote to 6 2 VNote B 4 OS for IBM PC The following OSs for IBM PC are supported When operating SM78K0 ID78K0 FE9200 See C 2 Fuzzy Inference Development Support System Windows Ver 3 0 to Ver 3 1 is necessary Note Only English mode is supported Caution MS DOS Ver 5 0 or later have a task swap function but this task swap function cannot be used in this software ...

Page 532: ...BK 78K I Series IE 78130 R IE 78140 R 78K II Series IE 78230 RNote IE 78230 R A IE 78240 RNote IE 78240 R A 78K III Series IE 78320 RNote IE 78327 R IE 78330 R IE 78350 R Note Available for maintenance purposes only Table B 2 System up Method from Other In Circuit Emulator to IE 78000 R A Series Name In circuit Emulator Owned Board to be Purchased 75X XL Series IE 75000 RNote 1 IE 75001 R IE 78000...

Page 533: ...E EV 9200GC 64 B D C M N L K R Q I H P O S T J G No 1 pin index EV 9200GC 64 G0 ITEM MILLIMETERS INCHES A B C D E F G H I J K L M N O P Q R S T 18 8 14 1 14 1 18 8 4 C 3 0 0 8 6 0 15 8 18 5 6 0 15 8 18 5 8 0 7 8 2 5 2 0 1 35 0 35 0 1 2 3 1 5 0 74 0 555 0 555 0 74 4 C 0 118 0 031 0 236 0 622 0 728 0 236 0 622 0 728 0 315 0 307 0 098 0 079 0 053 0 014 0 091 0 059 0 004 0 005 φ φ φ φ ...

Page 534: ... 36 0 03 2 2 0 1 1 57 0 03 0 768 0 583 0 583 0 768 0 236 0 236 0 197 0 093 0 087 0 062 0 8 0 02 15 12 0 0 05 0 8 0 02 15 12 0 0 05 φ φ φ 0 002 0 001 0 003 0 002 0 002 0 001 0 003 0 002 0 004 0 003 0 004 0 003 0 001 0 002 φ φ φ 0 001 0 002 0 004 0 005 0 001 0 002 Caution Dimensions of mount pad for EV 9200 and that for target device QFP may be different in some parts For the recommended mount pad d...

Page 535: ...taSheet4U com APPENDIX C EMBEDDED SOFTWARE 535 APPENDIX C EMBEDDED SOFTWARE The following embedded software are available for efficient program development and maintenance of the µPD78014 and 78014Y Subseries ...

Page 536: ... Outline Maximum number for use in mass production 001 Evaluation object Do not use for mass producing product 100K Mass production object 100 000 001M 1 000 000 010M 10 000 000 S01 Source program Source program of mass production object Host Machine Operating System Supply Medium 5A13 PC 9800 series MS DOS 3 5 inch 2HD 5A10 Ver 3 30 to 5 inch 2HD Ver 6 2Note 7B13 IBM PC AT and See B 4 3 5 inch 2H...

Page 537: ...ape QIC 24 3P16 HP9000 series 700 HP UX Rel9 01 Digital audio tape DAT 3K15 SPARCstation SunOS Rel4 1 1 Cartridge tape QIC 24 3M15 EWS4800 series RISC EWS UX V Rel4 0 C 1 Real time OS 2 2 MX78K0 MX78K0 is a subset OS which is based on the µITRON specification Supplied with the MX78K0 OS nucleus MX78K0 OS controls tasks events and time In task control MX78K0 OS controls task execution order and the...

Page 538: ...e is executed by linking fuzzy knowledge data Fuzzy converted by translator Inference Module Part Number µS FI78K0 PC 9800 series IBM PC AT and compatible machine FD78K0 Support software evaluating and adjusting fuzzy knowledge data at hardware level by using Fuzzy Inference in circuit emulator Debugger Part Number µS FD78K0 PC 9800 series IBM PC AT and compatible machine Remark of the part number...

Page 539: ...r register 1 TM1 207 8 bit timer register 2 TM2 207 External interrupt mode register INTM0 184 455 I Internal memory size switching register IMS 495 Interrupt mask flag register 0H MK0H 453 470 Interrupt mask flag register 0L MK0L 453 Interrupt request flag register 0H IF0H 452 470 Interrupt request flag register 0L IF0L 452 Interrupt timing specification register SINT 276 295 314 330 356 375 388 ...

Page 540: ...r 0 SIO0 269 327 Serial I O shift register 1 SIO1 412 Serial operating mode register 0 CSIM0 271 277 278 291 311 330 338 339 352 372 384 Serial operating mode register 1 CSIM1 415 418 419 422 16 bit capture register CR01 177 16 bit compare register CR00 177 16 bit timer mode control register TMC0 180 16 bit timer output control register TOC0 182 16 bit timer register TM0 177 16 bit timer register ...

Page 541: ... 384 CSIM1 Serial operating mode register 1 415 418 419 422 I IF0H Interrupt request flag register 0H 452 470 IF0L Interrupt request flag register 0L 452 IMS Internal memory size switching register 495 INTM0 External interrupt mode register 184 455 K KRM Key return mode register 151 471 M MK0H Interrupt mask flag register 0H 453 470 MK0L Interrupt mask flag register 0L 453 MM Memory expansion mode...

Page 542: ... register 0 269 327 SIO1 Serial I O shift register 1 412 SVA Slave address register 269 327 T TCL0 Timer clock select register 0 178 240 TCL1 Timer clock select register 1 207 TCL2 Timer clock select register 2 224 234 244 TCL3 Timer clock select register 3 271 330 413 TM0 16 bit timer register 177 TM1 8 bit timer register 1 207 TM2 8 bit timer register 2 207 TMC0 16 bit timer mode control registe...

Page 543: ...sing port 1 as A D converter input was added CHAPTER 4 Cautions on port mode register setting when port 2 is used in the SBI mode was PORT FUNCTIONS added Cautions on port mode register setting was added Cautions on pull up resistor option register when port is used as dual function pin was added Cautions on CR00 setting was added CHAPTER 6 16 BIT Timing chart for square wave output operation was ...

Page 544: ...r slave device is in the busy state or not when device is in the master mode was added in section 13 4 2 Cautions on SBI mode Section 13 4 4 I2 C bus mode operation was added Block diagram for serial interface channel 1 was changed CHAPTER 14 Format of the serial operating mode register 1 was changed SERIAL INTERFACE Timing chart for 3 wire serial I O mode was corrected CHANNEL 1 Timing chart and ...

Page 545: ...ait release slave reception 4 Reception completion CHANNEL 0 processing by a slave µPD78014Y Subseries Section 16 4 7 Restrictions on Use of I2 C Bus Mode was added Sections 20 2 Operation Codes and 20 3 Descriptions of Instructions in CHAPTER 23 previous edition were deleted INSTRUCTION SET 6th Figure 11 3 Watchdog Timer Mode Register Format was changed and cautions CHAPTER 11 for the figure were...

Page 546: ...rface Channel 0 Control Register SERIAL INTERFACE 2 Serial operating mode register 0 CSIM0 CHANNEL 0 µPD78014Y Cautions were added in section 16 4 3 2 a Bus release signal REL b Subseries Command signal CMD 11 Cautions on SBI mode Item 3 MSB LSB switching as the start bit was added in section 17 4 2 3 wire CHAPTER 17 serial I O mode operation SERIAL INTERFACE 3 d Busy control option e Busy strobe ...

Page 547: ... 719 5951 Address North America NEC Electronics Inc Corporate Communications Dept Fax 1 800 729 9288 1 408 588 6130 Europe NEC Electronics Europe GmbH Technical Documentation Dept Fax 49 211 6503 274 South America NEC do Brasil S A Fax 55 11 6465 6829 Asian Nations except Philippines NEC Electronics Singapore Pte Ltd Fax 65 250 3583 Japan NEC Corporation Semiconductor Solution Engineering Division...

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NEC 78011BGC AB8 Series, User Manual

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