July
2009
Rev
0.06
Page 15 of 31
4.1.3
Video Pass-through Tests
In Pass-through Mode the EVK uses the clock recovered by the LMH0341 from the SDI input as the reference
clock. The video data is then routed through the FPGA to the LMH0340 for transmission. To configure the EVK
for Pass-through Mode connect the source generator to J13 of the deserializer and connect the terminating
device to the serializer BNC connector J8. Refer to the diagram below. The loop through driver can also be
connected to the terminating device via BNC connector J10.
Figure 12 Pass-through Test Setup
4.2
Terminal Based SD/HD/3G SDI Evaluation
Below the terminal greeting message is the main menu. The table below gives a brief description of the main
menu options.
Table 3 Terminal Menu Options
Menu Option
Name
Function
1
I2C Read
Read from a device register.
2
I2C Write
Write to a device register.
3
Register Read
Read from an FPGA register.
4
Register Write
Write to an FPGA register.
5
I2C Bus Scan
Returns 7-bit address of all devices on the serial control bus.
6
Put System in
Standalone Mode
Configures system for Standalone Mode. Accesses format select
menu.
7
Put System in Analog
Sync TPG mode
Generates clock from Analog sync input and uses this to drive Test
Pattern Generator
8
Put System in Analog
Sync Reclock Mode
When supplied with an Analog Sync and a synchronous SDI input,
the system uses the gunlock feature of the LMH1982 to reclock the
SDI video with a clock derived from the analog input.
9
Put System in Analog
Sync Alternate TPG
mode
Generates Test patterns synchronized to the SDI input.
A SDI
Passthrough
Mode
SDI video is received by the LMH0341, analysed and retransmitted,
using the clock recovered from the LMH0341.