July
2009
Rev
0.06
Page 26 of 31
Hex Address: Name
Description
Bits
Bit Description
001 1
Sweep (not implemented)
010 2
Calculated Patterns
011 3
Pulse/Bar
100 4
RP219 Pattern
101 5
SMPTE Bars
Others
100% Color Bars
1B SMPTE
352
INSERT
CONTROL
Allows bytes 3 and 4 of the
SMPTE352 packet to be set
15:8
7:0
Byte 4
Byte 3
1C LINE
PATTERN
UPDATE 1
16 MSB for line pattern
update
15:0 Update
Value
1D LINE
PATTERN
UPDATE 2
16 LSB for line pattern
update
15:0 Update
Value
1E LINE
PATTERN
UPDATE ADDR
Adress and write enable for
pattern update
15
14:11
10:0
Write Enable
Reserved
Update adress
5.1.5 Clocking
Hex Address: Name
Description
Bits
Bit Description
20 CLOCK
STATUS:
ALTERA
Status of ALtera PLLs
15:3
2
1
0
Reserved
Active clock: specified whether
the receive (0) or PLL (1) clock
is for transmission
Tx PLL Locked
Rx PLL Locked
21 CLOCK
CONTROL:
ALTERA
Control Altera Clock
selection
15
14:0
Select PLL (1) or Rx (0) Clock
Reserved
5.1.6 Video
Timing
Hex Address: Name
Description
Bits
Bit Description
23 CONTROL
GENLOCK
Control Genlock Mode
15:2
1:0
Reserved
Select System Mode:
00 0
Use Received Video
Timing
01 1
Use Genlock timing
10 2
Freerun/User specified
timing
11 3
Use Genlock timing with
user specified format
24 GENLOCK
STATUS
Status of Gunlock Interface
15
14:12
Progressive video on reference
SD HD 3G Format
