July
2009
Rev
0.06
Page 8 of 31
2.3
SDALTEVK Board Description
The HSMC SDI ADAPTER board features the 5:1 LMH0340 serializer IC with integrated cable driver, the 1:5
LMH0341 deserializer IC and the LMH0344 adaptive cable equalizer IC, all highlighted in orange. These devices
support SD, HD, or 3G SDI interfaces across 75 ohm coaxial cable, which can interface with the board via BNC
connectors J3, J8, J10, or J13.
For added testing flexibility, the additional components shown in blue allow for several different clocking schemes.
All of the clocking schemes are controlled by the DS90CP22 which is used to multiplex the various clock sources
to the FPGA. The LMH1981 receives analog video via BNC connector J2 and provides the HSYNC and VSYNC
to the LMH1982 for clock generation. The LMH1982 can also generate a clock based on a local 27 MHz
oscillator. By using the DS90LV031A, an external clock can be applied to the card at SMA connector J4. In order
to observe the quality of the clock provided to the FPGA, the clock can be routed to the DS90LV028A which will
drive a CMOS clock out of SMA connector J5.
Power is provided to the board via two separate power rails that travel across the HSMC connector from the
Cyclone III host board. The Powerwise® LM20242 adjustable frequency synchronous buck regulator supplies the
3.3V power for the evaluation card by using the 12V rail from the host board. The LP3878ADJ low noise regulator
uses the 3V power of the host board to supply the 2.5V power to the evaluation card.
Figure 6 SDALTEVK
