DS25CP104EVK User Manual
For descriptive purposes the DS25CP104EVK can be broken into three parts:
1. The
DS25CP104
IC with associated connectors and jumpers is the main part of the
board. The block diagram of the DS25CP104 is shown in Figure 3. The receive buffers
can be set to Off and Low equalization by the external pins EQ0 – EQ3; the transmit
buffers can be set to Off and Med. levels of pre-emphasis by the external pins PE0 – PE3.
Since data capabilities are 3.125 Gbps, SMA connectors are used to ensure minimal loss.
More information can be found about the DS25CP104 on the data sheets.
2. A
USB to SMBus converter
has been added to the evaluation kit to implement
SMBus switch configuration to control the signal conditioning. Through the SMBus the
DS25CP104 currently features four levels (Off, Low, Medium, and High) of pre-
emphasis and two levels (Off, Low) of equalization.
3.
Three channels of stripline
have been added to the evaluation kit to test the pre-
emphasis and equalization functions (15” (38.1cm), 30” (76.2cm), and 60” (152.4cm) ).
In practical applications, devices often drive long backplanes or cables. To help reduce
jitter caused from long backplanes or cables, pre-emphasis can be used for the drivers and
equalization for the receivers.
SD
A
SCL
EN
_s
mb
A
DDRn
Figure 3
. DS25CP104 Block Diagram
Page 5 of 17
Summary of Contents for DS25CP104
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