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National Semiconductor DS25CP104, User Manual

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Summary of Contents for DS25CP104

Page 1: ...ansmit Pre emphasis and Receive Equalization DS25CP104 Evaluation Kit USER MANUAL Part Number DS25CP104EVK For the latest documents concerning these products and evaluation kit visit lvds national com Schematics and gerber files are also available at lvds national com ...

Page 2: ...DS25CP104EVK User Manual Table of Contents Table of Contents 2 Overview 3 DS25CP104 EVK Description 4 CP104 Evaluation 6 SMBus Evaluation 12 Typical Performance 16 Page 2 of 17 ...

Page 3: ...phasis or equalization a USB to SMBus conversion circuit to control the SMBus with a PC and three FR4 striplines 15 38 1cm 30 76 2cm and 60 152 4cm to exercise the devices signal conditioning features pre emphasis and equalization The purpose of this document is to familiarize the user with the DS25CP104EVK to suggest test setup procedures and instrumentation to test the device optimally and to gu...

Page 4: ...04EVK Description Figure 2 shows the top layer drawing of the PCB with the silkscreen annotations The 4 5 by 4 5 inch eight layer PCB is designed to evaluate the functions of the DS25CP104 Figure 2 Top Layer DS25CP104EVK Page 4 of 17 ...

Page 5: ...bout the DS25CP104 on the data sheets 2 A USB to SMBus converter has been added to the evaluation kit to implement SMBus switch configuration to control the signal conditioning Through the SMBus the DS25CP104 currently features four levels Off Low Medium and High of pre emphasis and two levels Off Low of equalization 3 Three channels of stripline have been added to the evaluation kit to test the p...

Page 6: ...l jumpers on the evaluation board in the Pin Mode Initial Pin Settings for Pin Mode Testing Pin Setting Note SMBus Enable L Disable SMbus EQ0 EQ 3 L Equalization off See table PE0 PE3 L Pre Emphasis off See table PWDN H Power Down off Switch Configuration Truth Tables S01 S00 Input Selected 0 0 IN0 0 1 IN1 1 0 IN2 1 1 IN3 Table 1 Input Select Pins Configuration for the Output OUT0 S11 S10 Input Se...

Page 7: ... Conditioning Tables Output OUTn n 0 1 2 3 Pre Emphasis Control Pin PEn State Pre Emphasis Level 0 Off 1 Medium Table 5 Transmit Pre emphasis Truth Table Input INn n 0 1 2 3 Equalization Control Pin EQn State Equalization Level 0 Off 1 Low Table 6 Receive Equalization Truth Table Stripline Length Table also known as Test Channels Stripline Length Loss dB 1250 MHz L1 15 38 1cm 3 6 L2 30 76 2cm 8 2 ...

Page 8: ... and 6 4 Apply supply 3 3V typical to the VDD and supply ground to the VSS connectors 5 Connect a signal source signal generator data source or an LVDS driver to the desired INn inputs on the board and adjust the signal parameters VOH VOL VCM so that they comply with the device input recommendations 6 Connect an oscilloscope to the selected OUTn outputs and view the output signals with an oscillos...

Page 9: ...Tn drivers by selecting S00 S01 S10 S11 S20 S21 according to Tables 1 4 3 Select the PEn jumpers to 1 and the EQn jumpers to 0 according to Tables 5 and 6 4 Apply supply 3 3V typical to the VDD and supply ground to the VSS connectors 5 Connect a signal source signal generator data source or an LVDS driver to the desired INn inputs on the board and adjust the signal parameters VOH VOL VCM so that t...

Page 10: ...rs by selecting S00 S01 S10 S11 S20 S21 S30 S31 according to Tables 1 4 3 Select the PEn jumpers to 0 and the EQn jumpers to 1 according to Tables 5 and 6 4 Apply supply 3 3V typical to the VDD and supply ground to the VSS connectors 5 Connect a signal source signal generator data source or an LVDS driver to the desired INn inputs on the board and adjust the signal parameters VOH VOL VCM so that t...

Page 11: ...les 1 4 3 Select the PEn jumpers to 1 and the EQn jumpers to 1 according to Tables 5 and 6 4 Apply supply 3 3V typical to the VDD and supply ground to the VSS connectors 5 Connect a signal source signal generator data source or an LVDS driver to the desired INn inputs on the board and adjust the signal parameters VOH VOL VCM so that they comply with the device input recommendations 6 Connect an os...

Page 12: ...www national com appinfo lvds ds25cp104evk html Place in any folder on your PC and run the file by double clicking on the file from Windows Explorer or My Computer this will extract the file and place it in C Program Files National Semiconductor Corp folder The Analog Launch Pad will now function only in the Demo mode The Analog Launch Pad is designed to function on Windows 98 2000 xp Setup the CP...

Page 13: ...d should be in communication with the PC this can be known by Hi speed USB device plugged into non Hi Speed USB hub appearing in the window Follow the instructions for New Hardware Wizard which may take up to one minute to run a select Install from a list or specific location b select Don t search I will choose the driver to install c select Have disk d Browse to C Program Files National Semicondu...

Page 14: ...DS25CP104EVK User Manual Page 14 of 17 ...

Page 15: ...s to test their designs and systems using National s evaluation boards the CP104EVK interface has been designed into the Analog Launch Pad The registers of the CP104 can be accessed through this interface enabling all the functions accessed through the SMBus Below is a picture of the Analog Launch Pad CP104 interface Figure 8 Analog Launch Pad CP104 interface Page 15 of 17 ...

Page 16: ...pply Register descriptions can be found in the DS25CP104 datasheets Use only Apply to make changes Refresh Refresh All Display Load and Save bubbles should not be used A selected square corresponds to a 1 while a blank square corresponds to a 0 To change the levels of Pre Emphasis or Equalization you must first go to Control register and enable Ignore External PE and Ignore External EQ before adju...

Page 17: ...m with no STRIPLINE connected and with PE EQ Off The DS25CP104 3 125 Gbps PRBS 7 output eye diagram after the STRIPLINE 1 15 FR4 and with EQ Low See Figure 6 for the Setup used The DS25CP104 3 125 Gbps PRBS 7 output eye diagram before the STRIPLINE2 30 FR4 and with PE EQ Off The DS25CP104 3 125 Gbps PRBS 7 output eye diagram before the STRIPLINE 2 30 FR4 and with PE Med See Figure 5 for the Setup ...

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Page 20: ...03 PANA 10K 1 10W 5 0603 200ppm Pb Free 5 X 0 R3 8 9 12 13 ALT CRCW060310K0JNEA VISHAY 10K 1 10W 5 0603 200ppm Pb Free ALT RK73B1JTTD103J KOA 10K 1 10W 5 0603 200ppm Pb Free 11 RES ERJ 3GEYJ220 PANA 22 Ohm 1 10W 5 0603 200ppm Pb Free 2 X 0 R1 2 ALT CRCW060322R0JNEA VISHAY 22 Ohm 1 10W 5 0603 200ppm Pb Free ALT RK73B1JTTD220J KOA 22 Ohm 1 10W 5 0603 200ppm Pb Free 12 RES ERJ 3GEYJ222 PANA 2 2K 1 10...

Page 21: ...X7R Pb Free 19 20 FILTER MMZ1608R301A TDK Ferrite 300 Ohm 5A 0603 Pb Free 2 X 0 FB1 2 21 22 XTAL HCM49 24 000MABJ CITIZEN Crystal 24 0000MHz SMD 18pF Pb Free 1 X 0 Y1 23 24 FUSE 1206L050 LF 5A Resettable SMT 09 Ohms Pb Free 1 X 0 F1 25 26 CONN 1287 ST KEYSTONE Faston Male 250x 032 Pb Free 2 0 J25 26 27 CONN 142 0701 851 EMERSON SMA Jack Receptacle 50 OHM Pb Free 28 0 SMA1 28 28 CONN 61729 0010 FCI...

Page 22: ...DWG DS25CP104EVK 0 37 REF C 05888R0 ENERCON PALLET DWG DS25CP104EVK 0 38 REF S 05887R0 ENERCON SCHEMATIC DS25CP104EVK 0 39 40 41 Notes DO NOT STUFF R15 16 17 18 19 J5 6 1 12 35 PM 4 20 2007 3 3 Page of Confidential and Proprietary This document is considered uncontrolled unless stamped otherwise Creation Date 3 28 2007 Responsible Eng Mgr Creator Arlene Fox PL Number Z3071 01 Rev 0 Rev Date 3 28 2...

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