Figure 6.
I/O Block Diagram
EXTERNAL REF/SCLK
CLK IN SMA
CH2 SMA
ADS54J69
Dual 16-bit, 500 MS/s
CH3 SMA
CH1 SMA
ADS54J69
Dual 16-bit, 500 MS/s
CH0 SMA
ANALOG INPUT
DC Coupled
Path
400 MHz
AA Filter
AC (Balun)
Coupled Path
DC Coupled
Path
400 MHz
AA Filter
AC (Balun)
Coupled Path
DC Coupled
Path
400 MHz
AA Filter
AC (Balun)
Coupled Path
DC Coupled
Path
400 MHz
AA Filter
AC (Balun)
Coupled Path
CLOCKING
Adapter Module
Connector
Note
Only one analog input path type is populated. Refer to ni.com and the device
specifications for more details.
Component-Level Intellectual Property (CLIP)
The LabVIEW FPGA Module includes component-level intellectual property (CLIP) for HDL
IP integration. FlexRIO devices support two types of CLIP: user-defined and socketed.
•
User-defined CLIP
allows you to insert HDL IP into an FPGA target, enabling VHDL
code to communicate directly with an FPGA VI.
•
Socketed CLIP
provides the same IP integration of the user-defined CLIP, but it also
allows the CLIP to communicate directly with circuitry external to the FPGA. Adapter
module socketed CLIP allows your IP to communicate directly with both the FPGA VI
and the external adapter module connector interface.
The PXIe-5763 ships with socketed CLIP items that add module I/O to the LabVIEW project.
PXIe-5763 Getting Started Guide
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© National Instruments
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11
Summary of Contents for PXIe-5763
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