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Unpacking the Kit

Notice

 

To prevent electrostatic discharge (ESD) from damaging the device, ground

yourself using a grounding strap or by holding a grounded object, such as your
computer chassis.

1.

Touch the antistatic package to a metal part of the computer chassis.

2.

Remove the device from the package and inspect the device for loose components or any
other sign of damage.

Notice

 

Never touch the exposed pins of connectors.

Note

 

Do not install a device if it appears damaged in any way.

3.

Unpack any other items and documentation from the kit.

Store the device in the antistatic package when the device is not in use.

PCIe-5774 Kit Contents

The following items are included in the device kit:

PCIe-5774

Documentation:

Maintain Forced-Air Cooling Note to Users

PCIe-5774 Getting Started Guide

 (this document)

PCIe-5774 Safety, Environmental, and Regulatory Information

Preparing the Environment

Ensure the environment in which you are using the PCIe-5774 meets the following
specifications.

Operating environment

Ambient temperature range

0 °C to 45 °C (Tested in accordance with
IEC-60068-2-1 and IEC-60068-2-2. Meets
MIL-PRF-28800F Class 3 low temperature
limit and MIL-PRF-28800F Class 4 high
temperature limit.)

Relative humidity range

10% to 90%, noncondensing (Tested in
accordance with IEC 60068-2-56.)

Pollution Degree

2

PCIe-5774 Getting Started Guide

  | 

© National Instruments

  | 

3

Summary of Contents for PCIe-5774

Page 1: ...e 5774 Kit Contents 3 Preparing the Environment 3 Installing the Software and Driver 4 Installing the PCIe 5774 4 Installing the Ferrite on the DIO Cable 5 PCIe 5774 Front Panel and Pinout 6 Configuri...

Page 2: ...Available at ni com manuals Contains information about the FPGA module front panel connectors and I O programming instructions and I O component level IP CLIP LabVIEW Examples Available in NI Example...

Page 3: ...ge when the device is not in use PCIe 5774 Kit Contents The following items are included in the device kit PCIe 5774 Documentation Maintain Forced Air Cooling Note to Users PCIe 5774 Getting Started G...

Page 4: ...or installation instructions and information about getting started with the LabVIEW FPGA Module Documentation for the LabVIEW FPGA Module is available at ni com manuals 3 Optional Install the LabVIEW...

Page 5: ...7 Connect the 6 pin PCI Express power connector from the power supply to the PCIe 5774 8 Replace any access panels on the computer case 9 Power on your computer Installing the Ferrite on the DIO Cable...

Page 6: ...rrite Bead Installation 1 2 1 Molex Nano Pitch I O connector 2 Ferrite PCIe 5774 Front Panel and Pinout PCIe 5774 Front Panel The following figure shows the PCIe 5774 front panel 6 ni com PCIe 5774 Ge...

Page 7: ...ont Panel PCIe 5774 AI 0 AI 1 REF CLK IN TRIG IN TRIG OUT DIO 5Vpp MAX 6V MAX 3 3V LVTTL 3V MAX The following table describes the signal connections for the PCIe 5774 PCIe 5774 Getting Started Guide N...

Page 8: ...Standard SMA female connector Analog input connection AI 1 REF CLK IN Standard SMA female connector Input for an external Reference Clock or Sample Clock TRIG IN Standard SMA female connector Analog...

Page 9: ...3 GND MGT Tx 2 MGT Tx 2 GND MGT Tx 3 MGT Tx 3 GND Reserved The following table lists the available pins on the DIO connector Signal Type Direction MGT Tx 0 3 1 Xilinx UltraScale GTH Output MGT Rx 0 3...

Page 10: ...e MAX toolbar The MAX self test performs a basic verification of hardware resources FlexRIO Examples FlexRIO includes several example applications for LabVIEW These examples serve as interactive tools...

Page 11: ...V 12 V GPIO Configuration GPIO MGTs Reference Clock Power Supplies Flash FPGA Triggers Clk 100 Gen3 x8 PCIe 12 V 3 3 V 12 V Clk 10 Module Clocking Synchronization PLL DRAM Bank 0 2 GB DRAM Bank 1 2 GB...

Page 12: ...Reference Clock Power Supplies Flash FPGA Triggers Clk 100 Gen3 x8 PCIe 12 V 3 3 V 12 V Clk 10 Module Clocking Synchronization PLL DRAM Bank 0 2 GB DRAM Bank 1 2 GB Synchronization Connector PCIe Conn...

Page 13: ...n FlexRIO devices support two types of CLIP user defined and socketed User defined CLIP allows you to insert HDL IP into an FPGA target enabling VHDL code to communicate directly with an FPGA VI Socke...

Page 14: ...are a Reference Clock and triggers between the PCIe 5774 and another PCI Express FlexRIO device You also can use the compact synchronization cable for PCIe and a RTSI adapter part number 147008A 01L t...

Page 15: ...nd of the compact synchronization cable for PCIe into the closest synchronization connector on the RTSI adapter 5 Connect one RTSI female connector on the RTSI cable to the RTSI male connector on the...

Page 16: ...system 2 Launch MAX and perform the self test again 3 Power off the chassis 4 Reinstall the failed module in a different slot 5 Power on the chassis 6 Perform the self test again Where to Go Next Refe...

Page 17: ...ct registration facilitates technical support and ensures that you receive important information updates from NI NI corporate headquarters is located at 11500 North Mopac Expressway Austin Texas 78759...

Page 18: ...ments EULAs and third party legal notices in the readme file for your NI product Refer to the Export Compliance Information at ni com legal export compliance for the NI global trade compliance policy...

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