National Instruments PCI-6281, User Manual

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Chapter 9 Digital Routing and Clock Generation
PXI Clock and Trigger Signals
PXI clock and trigger signals are only available on PXI/PXI Express devices.
PXI_CLK10
PXI_CLK10 is a common low-skew 10 MHz reference clock for synchronization of multiple
modules in a PXI measurement or control system. The PXI backplane is responsible for
generating PXI_CLK10 independently to each peripheral slot in a PXI chassis.
PXI Triggers
A PXI chassis provides eight bused trigger lines to each module in a system. Triggers may be
passed from one module to another, allowing precisely timed responses to asynchronous
external events that are being monitored or controlled. Triggers can be used to synchronize the
operation of several different PXI peripheral modules.
On M Series devices, the eight PXI trigger signals are synonymous with RTSI <0..7>.
Note that in a PXI chassis with more than eight slots, the PXI trigger lines may be divided into
multiple independent buses. Refer to the documentation for your chassis for details.
PXI_STAR Trigger
In a PXI system, the Star Trigger bus implements a dedicated trigger line between the first
peripheral slot (adjacent to the system slot) and the other peripheral slots. The Star Trigger can
be used to synchronize multiple devices or to share a common trigger signal among devices.
A Star Trigger controller can be installed in this first peripheral slot to provide trigger signals to
other peripheral modules. Systems that do not require this functionality can install any standard
peripheral module in this first peripheral slot.
An M Series device receives the Star Trigger signal (PXI_STAR) from a Star Trigger controller.
PXI_STAR can be used as an external source for many AI, AO, and counter signals.
An M Series device is not a Star Trigger controller. An M Series device may be used in the first
peripheral slot of a PXI system, but the system will not be able to use the Star Trigger feature.
PXI_STAR Filters
You can enable a programmable debouncing filter on each PFI, RTSI, or PXI_STAR signal.
When the filters are enabled, your device samples the input on each rising edge of a filter clock.
M Series devices use an onboard oscillator to generate the filter clock with a 40 MHz frequency.
Note NI-DAQmx
only
supports filters on counter inputs.
The following is an example of low to high transitions of the input signal. High to low transitions
work similarly.