National Instruments PCI-6281, User Manual

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B-28
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Appendix B Timing Diagrams
Digital I/O Timing Diagrams
This section describes the timing delays and requirements of digital waveform acquisitions and
digital waveform generations.
Digital Waveform Acquisition Timing
To describe digital waveform acquisition timing delays and requirements, refer to the circuitry
shown in Figure B-37. In the figure, P0, PFI, RTSI, and PXI_STAR represent signals at
connector pins of the M Series device. The other named signals represent internal signals.
Figure B-37. Digital Waveform Acquisition Timing Circuitry
Figure B-38 and Tables B-22 and B-23 describe the digital waveform acquisition timing delays
and requirements. Your inputs must meet the requirements to ensure proper behavior.
Figure B-38. Digital Waveform Acquisition Timing Delays
DO W a veform
Gener a tion FIFO
PFI (O u tp u t)
P0
DO Sa mple
Clock
Other Intern a l
S ign a l s
PFI_i, RT S I_i,
or PXI_ S TAR_i
PFI, RT S I,
or PXI_ S TAR
PFI, RT S I,
or PXI_ S TAR
PFI_i, RT S I_i,
or PXI_ S TAR_i
t
1
t
2
t
3
t
3
t
2
t
4
t
4
t
7
t
8
t
9
t
5
t
6
t
7
PFI (O u tp u t)
DI Sa mple Clock
P0
P0_i