National Instruments PCI-445 Series User Manual Download

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Contents

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Figures

The Relationship between the Programming Environment,
NI-DAQ, and Your Hardware............................................................... 1-5

Figure 3-1.

Digital Function Block Diagram........................................................... 3-1

Figure 3-2.

PCI-4451/4452 Analog Function Block Diagram ................................ 3-2

Figure 3-3.

PCI-4453/4454 Analog Function Block Diagram ................................ 3-3

Figure 3-4.

Below-Low-Level Triggering Mode..................................................... 3-9

Figure 3-5.

Above-High-Level Triggering Mode.................................................... 3-9

Figure 3-6.

Inside-Region Triggering Mode ........................................................... 3-10

Figure 3-7.

High-Hysteresis Triggering Mode ........................................................ 3-10

Figure 3-8.

Low-Hysteresis Triggering Mode......................................................... 3-10

Figure 3-9.

RTSI Bus Signal Connection ................................................................ 3-12

Figure 4-1.

Analog Pin Connections for the PCI-4451/4452 .................................. 4-2

Figure 4-2.

Analog Pin Connections for the PCI-4453/4454 .................................. 4-5

Figure 4-3.

Digital Pin Connections ........................................................................ 4-8

Figure 4-4.

Analog Input Stage of the PCI-4451/4452............................................ 4-12

Figure 4-5.

Analog Input Stage of the PCI-4453/4454............................................ 4-13

Figure 4-6.

Analog Output Channel Block Diagram for the PCI-4451................... 4-15

Figure 4-7.

Analog Output Channel Block Diagram for the PCI-4453................... 4-16

Figure 4-8.

Digital I/O Connections ........................................................................ 4-17

Figure 4-9.

Typical Posttriggered Acquisition ........................................................ 4-19

Figure 4-10.

Typical Pretriggered Acquisition .......................................................... 4-20

Figure 4-11.

EXTSTROBE* Signal Timing ............................................................. 4-22

Figure 4-12.

GPCTR0_SOURCE Signal Timing ...................................................... 4-23

Figure 4-13.

GPCTR0_OUT Signal Timing ............................................................. 4-24

Figure 4-14.

GPCTR1_SOURCE Signal Timing ...................................................... 4-25

Figure 4-15.

GPCTR1_OUT Signal Timing ............................................................. 4-26

Figure 4-16.

GPCTR Timing Summary .................................................................... 4-27

Figure 6-1.

Input Frequency Response .................................................................... 6-5

Figure 6-2.

Input Frequency Response Near the Cutoff.......................................... 6-6

Figure 6-3.

Alias Rejection at the Oversample Rate for the PCI-4451/4452 .......... 6-7

Figure 6-4.

Alias Rejection at the Oversample Rate for the PCI-4453/4454 .......... 6-8

Figure 6-5.

Comparison of a Clipped Signal to a Proper Signal ............................. 6-9

Figure 6-6.

Signal Spectra in the DAC .................................................................... 6-13

Figure A-1.

PCI-4451/4452 Idle Channel Noise (Typical) ...................................... A-5

Figure B-1.

DB-25 Pinout for the SHC68-DB25 Cable........................................... B-1

Figure B-2.

68-Pin Digital Connector for Any Digital Accessory........................... B-2

Summary of Contents for PCI-445 Series

Page 1: ...derutilized and idle equipment along with credit for buybacks and trade ins Custom engineering so your equipment works exactly as you specify Critical and expedited services Leasing Rentals Demos In stock Ready to ship TAR certified secure asset solutions Expert team I Trust guarantee I 100 satisfaction All trademarks brand names and brands appearing herein are the property of their respective own...

Page 2: ...DAQ PCI 4451 4452 4453 4454 User Manual Dynamic Signal Acquisition Device for PCI PCI 4451 4452 4453 4454 User Manual March 2000 Edition Part Number 321891B 01 ...

Page 3: ...rmany 089 741 31 30 Greece 30 1 42 96 427 Hong Kong 2645 3186 India 91805275406 Israel 03 6120092 Italy 02 413091 Japan 03 5472 2970 Korea 02 596 7456 Mexico D F 5 280 7625 Mexico Monterrey 8 357 7695 Netherlands 0348 433466 New Zealand 09 914 0488 Norway 32 27 73 00 Poland 0 22 528 94 06 Portugal 351 1 726 9011 Singapore 2265886 Spain 91 640 0085 Sweden 08 587 895 00 Switzerland 056 200 51 51 Tai...

Page 4: ...lure to follow the National Instruments installation operation or maintenance instructions owner s modification of the product owner s abuse misuse or negligent acts and power failure or surges fire flood accident actions of third parties or other events outside reasonable control Copyright Under the copyright laws this publication may not be reproduced or transmitted in any form electronic or mec...

Page 5: ... DAQ Driver Software 1 4 Optional Equipment 1 5 Custom Cabling 1 6 Analog Cables 1 6 Analog Accessories 1 7 Digital Cables PCI 4451 4452 Only 1 7 Chapter 2 Installation and Configuration Software Installation 2 1 Hardware Installation 2 1 Device Configuration 2 2 Chapter 3 Hardware Overview Analog Input 3 4 Input Mode 3 4 Input Coupling 3 4 Input Polarity and Input Range 3 4 Considerations for Sel...

Page 6: ...ignal Connections PCI 4451 4452 Only 4 17 Digital Power Connections PCI 4451 4452 Only 4 18 Timing Connections 4 18 Programmable Function Input Connections PCI 4451 4452 Only 4 19 Acquisition Timing Connections 4 19 PFI0 TRIG1 EXT_TRIG Signal 4 20 PFI1 TRIG2 PRETRIG Signal 4 21 CONVERT Signal 4 21 EXTSTROBE Signal PCI 4451 4452 Only 4 21 Waveform Generation Timing Connections 4 22 WFTRIG Signal 4 ...

Page 7: ...ion 5 3 Chapter 6 Theory of Analog Operation Functional Overview 6 1 Analog Input Circuitry 6 1 Input Coupling 6 3 Calibration 6 3 Antialias Filtering 6 3 The ADC 6 9 Noise 6 10 Analog Output Circuitry PCI 4451 4453 Only 6 11 Anti Image Filtering 6 12 The DAC 6 14 Calibration 6 14 Mute Feature 6 15 Appendix A Specifications Appendix B Pin Connections Appendix C Technical Support Resources Glossary...

Page 8: ...454 4 13 Figure 4 6 Analog Output Channel Block Diagram for the PCI 4451 4 15 Figure 4 7 Analog Output Channel Block Diagram for the PCI 4453 4 16 Figure 4 8 Digital I O Connections 4 17 Figure 4 9 Typical Posttriggered Acquisition 4 19 Figure 4 10 Typical Pretriggered Acquisition 4 20 Figure 4 11 EXTSTROBE Signal Timing 4 22 Figure 4 12 GPCTR0_SOURCE Signal Timing 4 23 Figure 4 13 GPCTR0_OUT Sign...

Page 9: ...ge and Resolution of the PCI 4451 3 7 Table 4 1 Analog I O Connector Pin Assignment for the PCI 4451 4452 4 3 Table 4 2 Analog I O Signal Summary for the PCI 4451 4452 4 4 Table 4 3 Analog I O Connector Pin Assignment for the PCI 4453 4454 4 6 Table 4 4 Analog I O Signal Summary for the PCI 4453 4454 4 7 Table 4 5 Digital I O Connector Pin Assignment 4 9 Table 4 6 Digital I O Signal Summary 4 11 ...

Page 10: ...se the manuals you have as follows Software documentation You may have both application software and NI DAQ software documentation National Instruments application software includes LabVIEW LabWindows CVI ComponentWorks Measure and VirtualBench After you set up your hardware system use either your application software documentation or the NI DAQ documentation to help you write your application Acc...

Page 11: ...o a key concept This font also denotes text that is a placeholder for a word or value that you must supply monospace Text in this font denotes text or characters that you should enter from the keyboard sections of code programming examples and syntax examples This font is also used for the proper names of disk drives paths directories programs subprograms subroutines device names functions operati...

Page 12: ...tal I O two 24 bit counter timers for timing I O and multiple triggering modes including external digital trigger See Appendix A Specifications for details about your PCI 445X The analog input and analog output circuitry both use oversampling delta sigma modulating converters Delta sigma converters are inherently linear provide built in brick wall anti aliasing imaging filters and have specificati...

Page 13: ...EW for Windows LabVIEW for Mac OS PCI 4451 4452 only LabWindows CVI for Windows VirtualBench DSA ComponentWorks Measure One of the following software packages and documentation NI DAQ for PC Compatibles NI DAQ for Mac OS PCI 4451 4452 only Your computer with an available PCI slot One of the following SHC68 C68 A1 analog cable SHC68 DB25 analog cable for OEM One of the following analog accessories ...

Page 14: ...program and use your National Instruments device You can use LabVIEW LabWindows CVI VirtualBench DSA ComponentWorks and Measure National Instruments Application Software LabVIEW and LabWindows CVI are innovative program development software packages for data acquisition and control applications LabVIEW uses graphical programming whereas LabWindows CVI enhances the C programing language Both packag...

Page 15: ...s a higher level programming interface for building virtual instruments with Visual Basic Visual C Borland Delphi and Microsoft Internet Explorer With ComponentWorks you can use all of the configuration tools resource management utilities and interactive control utilities included in NI DAQ Measure is a data acquisition and instrument control add in for Microsoft Excel With Measure you can acquire...

Page 16: ...ware Optional Equipment PCI 4451 4452 National Instruments offers a variety of products to use with your PCI 4451 4452 including these cables and connector blocks SHC50 68 digital cable Shielded and DIN rail mountable 68 pin connector blocks for digital I O RTSI cable for multiboard synchronization and triggering LabVIEW LabWindows CVI ComponentWorks or VirtualBench Conventional Programming Enviro...

Page 17: ...nstruments recommends using the SHC68 DB25 cable for those applications that require custom accessories The SHC68 DB25 cable a shielded 68 position VHDCI connector cabled to a standard DB 25 shell facilitates the creation of custom termination solutions PCI 4451 4452 Use shielded twisted pair wires for each differential analog input or output channel pair Since the signals are differential using t...

Page 18: ...8 position backshell with jackscrews part number 787191 1 Digital Cables PCI 4451 4452 Only To develop your own cable the mating connector for the digital I O is a 50 position receptacle For a connector pinout assignment refer to Figure 4 3 Digital Pin Connections and Table 4 5 Digital I O Connector Pin Assignment Recommended manufacturer part numbers for this mating connector are as follows 50 po...

Page 19: ...on software refer to your NI DAQ release notes and follow the instructions given there for your operating system and application software package Hardware Installation You can install the PCI 445X in any available PCI expansion slot in your computer However to achieve the best noise performance leave as much room as possible between the PCI 445X and other devices and hardware The following are gen...

Page 20: ... The PCI 445X devices are completely software configurable and require two types of configuration bus related and data acquisition related The PCI 445X devices are fully compatible with the industry standard PCI Local Bus Specification Revision 2 0 The PCI system automatically performs all bus related configurations and requires no interaction from you Bus related configuration includes setting th...

Page 21: ...s are shown in Figures 3 2 and 3 3 The digital and analog function blocks connect through the analog mezzanine bus Figure 3 1 Digital Function Block Diagram Direct Digital Synthesis Clock Generator DAQ STC AI FIFO MITE PCI Controller PCI Bus AO FIFO Parallel Serial Converter FIFO and DMA Control General Control Functions Clock Control RTSI Bus Digital I O Bus Analog Mezzanine Bus to Analog Section...

Page 22: ...ain AMP ADC2 AC DC Coupling MUX2 INPUT CAL MUX2 0 dB 20 dB ATTEN MUX2 DIFF Gain AMP ADC3 AC DC Coupling MUX3 INPUT CAL MUX3 0 dB 20 dB ATTEN MUX3 Analog Overrange Detect Gain Offset Calibration AC DC MUX Control INPUT CAL MUX Control ATTEN MUX Control Gain Control ADC Control ADC Clock Manager DAC Control Attenuation Control Output Enable DIFF ATTEN AMP DAC0 ENABLE0 Analog Bus DIFF ATTEN AMP DAC1 ...

Page 23: ...zanine Bus to Digital Section EXT Digital Trigger Serial Data Manager ADC0 ADC1 ADC2 AC DC Coupling MUX2 INPUT CAL MUX2 ADC3 AC DC Coupling MUX3 INPUT CAL MUX3 Gain Offset Calibration AC DC MUX Control INPUT CAL MUX Control ADC Control ADC Clock Manager DAC Control Output Enable DAC0 ENABLE0 Analog Bus DAC1 Gain Offset Calibration General Control DAC Clock Manager EEPROM PCI 4454 only PCI 4453 onl...

Page 24: ...he negative input from floating sources can improve the measurement quality by removing the common mode noise PCI 4453 4454 This device operates in SE mode using the BNC 2142 DSA accessory For more information refer to the BNC 2142 Installation Guide Input Coupling The PCI 445X has a software programmable switch that determines if a capacitor is placed in the signal path If the switch is set for D...

Page 25: ...nput Ranges PCI 4451 4452 The input range you select for the PCI 4451 4452 depends on the expected range of the incoming signal A large input range can accommodate a large signal variation but reduces the voltage resolution A smaller input range Table 3 1 Actual Input Range and Measurement Resolution of the PCI 4451 4452 Linear Gain Gain Input Range Resolution1 0 1 20 dB 42 4 V2 3 0518 mV2 0 316 1...

Page 26: ...nnections that exceed the rated input voltages can damage the computer and the connected equipment National Instruments is not liable for any damages resulting from such connections Analog Output PCI 4451 4453 Only The analog output section of the PCI 4451 4453 is software configurable You can select different analog output configurations through application software designed to control the PCI 44...

Page 27: ...o them they automatically retransmit the last data point they received If you are expecting the data to return to 0 V or any other voltage level you must append the data to make it do so PCI 4451 You can configure the range settings on each output channel independently The software programmable attenuation on these devices increases their overall flexibility by matching the output signal ranges to...

Page 28: ...rigger based on the input signal and the user defined trigger levels Any of the timing sections of the DAQ STC can use this level trigger including the analog input analog output RTSI and general purpose counter timer sections For example you can configure the analog input section to acquire a given number of samples after the analog input signal crosses a specific threshold Due to the nature of d...

Page 29: ...ures 3 4 through 3 8 You can set lowValue and highValue independently in the software In below low level triggering mode shown in Figure 3 4 the trigger is generated when the signal value is less than lowValue highValue is unused Figure 3 4 Below Low Level Triggering Mode In above high level triggering mode shown in Figure 3 5 the trigger is generated when the signal value is greater than highValu...

Page 30: ...eresis triggering mode the trigger is generated when the signal value is greater than highValue with the hysteresis specified by lowValue Figure 3 7 High Hysteresis Triggering Mode In low hysteresis triggering mode the trigger is generated when the signal value is less than lowValue with the hysteresis specified by highValue Figure 3 8 Low Hysteresis Triggering Mode highValue Trigger lowValue high...

Page 31: ...ital triggering PCI 4453 4454 With the PCI 4453 4454 you can use the SMB connector for dedicated external digital triggering PCI 4451 4452 4453 4454 Using digital triggering you can trigger the PCI 445X from any other National Instruments device that has the RTSI bus feature and resides on the same PCI bus You can connect the device through the RTSI bus cable An external digital trigger can also t...

Page 32: ...gital I O for general purpose use through the 50 pin connector You can individually configure each line for either input or output The hardware up down control for general purpose counters 0 and 1 connect onboard to DIO6 and DIO7 respectively Thus you can use DIO6 and DIO7 to control the general purpose counters The up down control signals are input only and do not affect the operation of the DIO ...

Page 33: ...ny of these timing signals are also available as outputs on the RTSI pins as indicated in the RTSI Triggers section of this chapter and on the PFI pins as indicated in Chapter 4 Signal Connections PCI 4453 PCI 4454 Your PCI 4453 4454 uses the RTSI bus to interconnect timing signals between devices The RTSI bus enables the PCI 4453 4454 to both control and be controlled by other devices Programmabl...

Page 34: ...kS s in 190 7 µS s increments worst case The two analog input channels of the PCI 4453 and the four input channels of the PCI 4454 are simultaneously sampled at any software programmable rate from 5 0 kS s to 51 2 kS s in 47 684 µS s increments worst case The devices use direct digital synthesis DDS technology so that you can choose the correct sample rate required for your application All the inp...

Page 35: ...o be a DC signal This situation is due to the sharp antialiasing filters that remove frequency components above the sampling frequency If you have a situation where this occurs simply increase the sample rate until it meets the requirements of the Nyquist Sampling Theorem For more information on the filters and aliasing refer to Chapter 6 Theory of Analog Operation Unlike other converter technolog...

Page 36: ...ect the digital I O signals to the shielded cable through a single 50 pin connector PCI 4453 4454 This device does not have a digital I O connector but instead has an SMB connector for external digital triggering I O Connectors Table 4 1 describes the pin assignments for the 68 pin analog I O connector Table 4 5 describes the 50 pin digital connector on the PCI 4451 4452 A signal description follo...

Page 37: ...ND NC AIGND NC AIGND NC AIGND NC AIGND ACH3 2 AIGND ACH2 2 AIGND ACH1 AIGND ACH0 DGND AOGND1 NC NC AOGND 1 DAC1OUT 1 AOGND 1 5 V AOGND 1 DAC0OUT 1 AIGND NC AIGND NC AIGND NC AIGND NC AIGND NC AIGND NC AIGND NC AIGND NC AIGND ACH3 2 AIGND ACH2 2 AIGND ACH1 AIGND ACH0 1 35 2 36 3 37 4 38 5 39 6 40 7 41 8 42 9 43 10 44 11 45 12 46 13 47 14 48 15 49 16 50 17 51 18 52 19 53 20 54 21 55 22 56 23 57 24 5...

Page 38: ...ailable only on the PCI 4451 DAC0OUT DAC0OUT Output Analog Output Channel 0 This pin supplies the analog inverting output channel 0 This pin is available only on the PCI 4451 DAC1OUT DAC1OUT Output Analog Output Channel 1 This pin supplies the analog non inverting output channel 1 This pin is only available on the PCI 4451 DAC1OUT DAC1OUT Output Analog Output Channel 1 This pin supplies the analog...

Page 39: ...00 pA AIGND AI DAC0OUT AO 22 Ω to DAC0OUT 4 55 kΩ to AOGND Short circuit to DAC0OUT ground 16 7 mA at 10 V DAC0OUT AO 22 Ω to DAC0OUT 4 55 kΩ to AOGND Short circuit to DAC0OUT ground 16 7 mA at 10 V DAC1OUT AO 22 Ω to DAC1OUT 4 55 kΩ to AOGND Short circuit to DAC1OUT ground 16 7 mA at 10 V DAC1OUT AO 22 Ω to DAC1OUT 4 55 kΩ to AOGND Short circuit to DAC1OUT ground 16 7 mA at 10 V AOGND AO DGND DIO...

Page 40: ...C CGND NC CGND NC CGND NC CGND AI_SHLD3 2 CGND AI_SHLD2 2 CGND AI_SHLD1 CGND AI_SHLD0 DGND CGND NC NC CGND DAC1OUT 1 CGND 5 V CGND DAC0OUT 1 CGND NC CGND NC CGND NC CGND NC CGND NC CGND NC CGND NC CGND NC CGND ACH3 2 CGND ACH2 2 CGND ACH1 CGND ACH0 1 35 2 36 3 37 4 38 5 39 6 40 7 41 8 42 9 43 10 44 11 45 12 46 13 47 14 48 15 49 16 50 17 51 18 52 19 53 20 54 21 55 22 56 23 57 24 58 25 59 26 60 27 6...

Page 41: ...s a separate purpose DAC0OUT AOGND Output Analog Output Channel 0 This pin supplies the analog non inverting output channel 0 This pin is available only on the PCI 4453 Analog Output Ground AOGND is the reference point for the analog output voltage DAC1OUT AOGND Output Analog Output Channel 1 This pin supplies the analog non inverting output channel 1 This pin is only available on the PCI 4453 Ana...

Page 42: ...k mAat V Rise Time ns Bias ACH 0 3 AI 1 MΩ inparallelwith 50 pF to AIGND 42 4 V 42 4 V 100 pA AO_SHLD 0 3 CGND DAC0OUT AO 22 Ω to AOGND Short circuit to ground 16 7 mA at 10 V DAC1OUT AO 22 Ω to AOGND Short circuit to ground 16 7 mA at 10 V AO_SHLD 0 1 DGND DIO 5 V DO 0 7 Ω Short circuit to ground 1 A AI Analog Input AO Analog Output DIO Digital Input Output DO Digital Output 400 V 400 V guarantee...

Page 43: ...of the 68 pin connector NC NC NC NC NC NC NC 5 V 5 V 5 V DIO3 DIO4 DIO2 DIO0 DIO6 DIO7 CONVERT PFI1 TRIG2 PRETRIG PFI3 GPCTR1_SOURCE GPCTR1_OUT PFI7 PFI6 WFTRIG PFI8 GPCTR0_SOURCE GPCTR0_OUT FREQ_OUT DGND DGND NC NC DGND 5 V NC NC DGND DIO5 DGND EXTSTROBE DGND DIO1 DGND RESERVED1 DGND PFI0 TRIG1 EXT_TRIG DGND PFI4 GPCTR1_GATE DGND UPDATE DGND PFI9 GPCTR0_GATE DGND 25 50 24 49 23 48 22 47 21 46 20 ...

Page 44: ...ND Input Output TRIG1 As an input this is a source for the data acquisition trigger As an output this signal can drive external applications to indicate that a trigger on the device has occurred TRIG1 is the start acquisition signal In LabVIEW referred to as AI Start Trigger for both input and output PFI1 TRIG2 PRETRIG DGND Input Output PFI1 TRIG2 PRETRIG As an input this is one of the PFIs As an ...

Page 45: ...ansition indicates the initiation of the waveform generation In LabVIEW referred to as AO Start Trigger for both input and output PFI7 DGND Input PFI7 This is one of the PFIs PFI8 GPCTR0_SOURCE DGND Input Output PFI8 Counter 0 Source As an input this is one of the PFIs As an output this is the GPCTR0_SOURCE signal This signal reflects the actual source connected to the general purpose counter 0 PF...

Page 46: ...u CONVERT DO 3 5 at Vcc 0 4 5 at 0 4 1 5 50 kΩ pu PFI3 GPCTR1_SOURCE DIO Vcc 0 5 3 5 at Vcc 0 4 5 at 0 4 1 5 50 kΩ pu PFI4 GPCTR1_GATE DIO Vcc 0 5 3 5 at Vcc 0 4 5 at 0 4 1 5 50 kΩ pu GPCTR1_OUT DO 3 5 at Vcc 0 4 5 at 0 4 1 5 50 kΩ pu UPDATE DO 3 5 at Vcc 0 4 5 at 0 4 1 5 50 kΩ pu PFI6 WFTRIG DIO Vcc 0 5 3 5 at Vcc 0 4 5 at 0 4 1 5 50 kΩ pu PFI7 DI Vcc 0 5 50 kΩ pu PFI8 GPCTR0_SOURCE DIO Vcc 0 5 3...

Page 47: ...t connecting AIGND to other earth connected grounds is not recommended AIGND is not directly available if you are using a BNC 2140 accessory Figure 4 4 shows a diagram of the analog input stage of your PCI 4451 4452 Figure 4 4 Analog Input Stage of the PCI 4451 4452 The analog input stage applies gain and common mode voltage rejection and presents high input impedance to the analog input signals c...

Page 48: ...l has a high output impedance greater than 1 kΩ and is floating you can use an SE configuration and tether the signal minus to AIGND to reduce common mode interference You can make the DIFF and SE connections through the BNC 2140 accessory PCI 4453 4454 Figure 4 5 shows a diagram of your PCI 4453 4454 analog input stage Figure 4 5 Analog Input Stage of the PCI 4453 4454 The analog input stage pres...

Page 49: ...u plug the computer into the same power system Nonisolated outputs of instruments and devices that plug into the building power system fall into this category The difference in ground potential between two instruments connected to the same building power system is typically between 1 and 100 mV but can be much higher if power distribution circuits are not properly connected For this reason Nationa...

Page 50: ... pair to AOGND is not the same the connection is unbalanced but the difference between the plus and minus terminals is still equal to the desired signal If the minus side is grounded the plus voltage is equal to the signal Conversely if the plus side is grounded the minus voltage is equal to the negative of the signal In all cases the difference is equal to the signal Connection of analog output s...

Page 51: ...e 4 7 Figure 4 7 Analog Output Channel Block Diagram for the PCI 4453 The analog output stage is single ended only This means that the devices or loads receiving signals should not have their signal returns connected to any earth connected grounds external to the PCI 4453 Analog Power Connections Two pins on the analog I O connector supply 5 V 4 65 to 5 25 VDC at 1 0 A from the computer power supp...

Page 52: ... or outputs Figure 4 8 shows signal connections for three typical digital I O applications Figure 4 8 Digital I O Connections Figure 4 8 shows DIO 0 3 configured for digital input and DIO 4 7 configured for digital output Digital input applications include receiving TTL signals and sensing external device states such as the state of the switch shown in Figure 4 8 Digital output applications includ...

Page 53: ...d PFI0 through PFI9 excluding PFI2 and PFI5 and through the RTSI bus See Figure 3 9 RTSI Bus Signal Connection for a list of these signals These signals are explained in detail in the next section Programmable Function Input Connections PCI 4451 4452 Only Most of these PFIs are bidirectional As outputs they are not programmable and reflect the state of acquisition waveform generation and general p...

Page 54: ...olling The detection requirements for each timing signal are listed within the section that discusses that individual signal In edge detection mode the minimum pulse width required is 10 ns This applies for both rising edge and falling edge polarity settings There is no maximum pulse width requirement in edge detect mode In level detection mode there are no minimum or maximum pulse width requireme...

Page 55: ...election for either rising or falling edge The selected edge of the PFI0 TRIG1 signal starts the data acquisition sequence for both posttriggered and pretriggered acquisitions The PCI 4451 4452 supports analog level triggering on the PFI0 TRIG1 pin See Chapter 3 Hardware Overview for more information on analog level triggering As an output the PFI0 TRIG1 signal reflects the action that initiates a...

Page 56: ... TRIG2 is received the device acquires a fixed number of scans and the acquisition stops After PFI1 TRIG2 is received any additional PFI1 TRIG2 signals are ignored until the acquisition is restarted This mode acquires data both before and after receiving PFI1 TRIG2 As an output the PFI1 TRIG2 signal reflects the posttrigger in a pretriggered acquisition sequence This is true even if the acquisitio...

Page 57: ... the WFTRIG signal starts the waveform generation for the DACs As an output the WFTRIG signal reflects the trigger that initiates waveform generation This is true even if the waveform generation is externally triggered by another PFI signal The output is an active high pulse with a pulse width of 50 to 100 ns This output is set to high impedance at startup UPDATE Signal The UPDATE signal is only a...

Page 58: ...iming requirements for the GPCTR0_SOURCE signal Figure 4 12 GPCTR0_SOURCE Signal Timing The maximum allowed frequency is 20 MHz with a minimum pulse width of 23 ns high or low There is no minimum frequency limitation The 20 MHz or 100 kHz timebase normally generates the GPCTR0_SOURCE signal unless you select an external source GPCTR0_GATE Signal Any PFI pin can receive as an input the GPCTR0_GATE ...

Page 59: ...hows the timing of the GPCTR0_OUT signal Figure 4 13 GPCTR0_OUT Signal Timing GPCTR0_UP_DOWN Signal PCI 4451 4452 Only You can input this signal on the DIO6 pin It is not available as an output on the I O connector The general purpose counter 0 counts down when this pin is at a logic low and counts up when it is at a logic high You can disable this input so that software can control the up down fu...

Page 60: ...select some external source GPCTR1_GATE Signal PCI 4451 4452 Only Any PFI pin can receive as an input the GPCTR1_GATE signal which is available as an output on the PFI4 GPCTR1_GATE pin As an input the GPCTR1_GATE signal is configured in edge detection mode You can select any PFI pin as the source for GPCTR1_GATE and configure the polarity selection for either rising or falling edge You can use the...

Page 61: ... requirements for the GPCTR1_OUT signal Figure 4 15 GPCTR1_OUT Signal Timing GPCTR1_UP_DOWN Signal PCI 4451 4452 Only This signal can be received as an input on the DIO7 pin and is not available as an output on the I O connector General purpose counter 1 counts down when this pin is at a logic low and counts up at a logic high You can disable this input so that software can control the up down fun...

Page 62: ... SOURCE signal The GATE signal must be valid either high or low for at least 10 ns before the rising or falling edge of a SOURCE signal for the GATE to take effect at that SOURCE edge as shown by tgsu and tgh in Figure 4 16 It is not necessary to hold the GATE signal after the active edge of the SOURCE signal is detected If you use an internal timebase clock you cannot synchronize the GATE signal ...

Page 63: ...accuracy of measurements made with your PCI 445X if you do not take proper care when running signal wires between signal sources and the device For more information refer to National Instruments Application Note 025 Field Wiring and Noise Considerations for Analog Signals The following recommendations apply mainly to analog input signal routing to the device although they also apply to signal rout...

Page 64: ...this type of wire the signals attached to the ACHx and ACHx inputs are twisted together and then covered with a shield You then connect this shield only at one point to the signal source ground This kind of connection is required for signals traveling through areas with large magnetic fields or high electromagnetic interference The following recommendations apply for all digital signal connections...

Page 65: ... offset and gain errors The four levels of calibration available are described in this chapter The first level is the fastest easiest and least accurate whereas the last level is the slowest most difficult and most accurate Loading Calibration Constants Your PCI 445X device is factory calibrated at approximately 25 C to the levels indicated in Appendix A Specifications Before shipment the associat...

Page 66: ...arily in relative measurements you can ignore a small amount of gain error and self calibration should be sufficient If you calibrate your PCI 4451 4452 while it is connected to a BNC 2140 accessory set each input channel to SE and connect each channel terminal to a channel terminal through a BNC shunt In addition make sure that ICP power is turned off on the BNC 2140 to avoid affecting the refere...

Page 67: ...re this type of recalibration every year If you require factory recalibration send your PCI 445X back to National Instruments National Instruments will send the device back to you with a new calibration certificate Please check with National Instruments for additional information such as cost and delivery times If your company has a metrology laboratory you can recalibrate the PCI 445X at your loc...

Page 68: ...CI 4451 has two identical analog input channels The PCI 4452 has four identical analog input channels An analog input channel is illustrated in Figure 4 4 Analog Input Stage of the PCI 4451 4452 These input channels have 16 bit resolution and are simultaneously sampled at software programmable rates from 5 to 204 8 kS s in 190 7 µS s increments This flexibility in sample rates makes the device wel...

Page 69: ...the range of the ADCs Then digital antialiasing filters automatically adjust their cutoff frequency to remove frequency components above half the programmed sampling rate These filters cause a delay of 42 conversion periods between the input analog data and the digitized data The 95 dB dynamic range of the PCI 445X is the result of low noise and distortion and makes possible high accuracy measurem...

Page 70: ... usually made during offset calibration which is described in Chapter 5 Calibration Calibration The PCI 445X analog inputs have calibration adjustments Onboard calibration DACs remove the offset and gain errors for each channel For complete calibration instructions refer to Chapter 5 Calibration Antialias Filtering A sampling system such as an ADC can represent signals of only limited bandwidth Sp...

Page 71: ...als go into the sampler a lowpass filter is applied to signals before they reach the sampler The PCI 445X includes two stages of anti alias filtering in each input channel lowpass filter This filter has a cutoff frequency of about 4 MHz and a rejection of greater than 40 dB at 20 MHz Because its cutoff frequency is significantly higher than the data sample rate the analog filter has an extremely f...

Page 72: ... frequency or within one Nyquist bandwidth of multiples of 128 times the sample rate The analog filter in each channel rejects possible aliases mostly noise from signals that lie near these multiples Figures 6 1 and 6 2 show the frequency response of the PCI 445X input circuitry Figure 6 1 Input Frequency Response Amplitude dB Frequency Sample Rate fs 0 00 20 00 40 00 60 00 80 00 100 00 120 00 0 0...

Page 73: ...s aliased into the passband region of the digital filter and is not attenuated The purpose of the analog filter is to remove these higher frequency components near multiples of the oversampling rate before they get to the sampler and the digital filter While the frequency response of the digital filter scales in proportion to the sample rate the frequency response of the analog filter remains fixe...

Page 74: ...for the PCI 4453 4454 in Figure 6 4 For frequencies not near multiples of the oversample rate the rejection is better than 85 dB Figure 6 3 Alias Rejection at the Oversample Rate for the PCI 4451 4452 Alias Rejection dB Over Sample Frequency 0 00 10 00 20 00 30 00 40 00 50 00 60 00 70 00 80 00 1 kS s 10 kS s 100 kS s 1 MS s Sample Rate 128 kHz 1 28 MHz 12 8 MHz 128 MHz 5 kS s 640 kHz ...

Page 75: ...ata to have high frequency energy This energy is spread throughout the frequency spectrum and because the clipping happens after the antialiasing filters the energy is aliased back into the baseband The remedy for this problem is simple do not allow the signal to exceed the nominal input range Figure 6 5 shows the spectra of 10 5 Vrms and 10 0 Vrms 3 0 kHz sine waves digitized at 48 kS s The signa...

Page 76: ...wn as delta sigma modulation If the data rate is 51 2 kS s each ADC actually samples its input signal at 6 5536 MS s 128 times the data rate and produces 1 bit samples that are applied to the digital filter This filter then expands the data to 16 bits rejects signal components greater than 25 6 kHz the Nyquist frequency and resamples the data at the more conventional rate of 51 2 kS s Although a 1...

Page 77: ...of the PCI 445X has a noise level of about 0 65 LSB rms this amount fluctuates The ratio of 23 170 475 0 65 is about 35647 or 91 0 dB the dynamic range but several factors can degrade the noise performance of the inputs One of these factors is noise picked up from nearby electronic devices The PCI 445X works best when it is kept as far away as possible from other plug in devices power supplies dis...

Page 78: ...input and output sample clocks are synchronized and derived from the same DDS clock The input and output clocks can differ from each other by a factor of 2 1 2 4 8 128 while still maintaining their synchronization Output conversions occur simultaneously at software programmable rates from 1 25 to 51 2 kS s in increments of 47 684 µS s The analog output circuitry uses eight times oversampling inter...

Page 79: ...ring in two stages First the data is digitally resampled at eight times the original sample rate then a linear phase digital filter removes almost all energy above one half the original sample rate and sends the data at the eight times rate to the DAC as shown in Figure 6 6b Some further inherent filtering occurs at the DAC because the data is digitally sampled and held at eight times the sample r...

Page 80: ...al Images a Spectrum of Sampled Signal b Spectrum of Signal After Digital Filter Frequency Amplitude F s 8 Fs 16 Fs Baseband Signal Images After the Digital Filter Frequency Amplitude Amplitude c Spectrum of Signal After DAC Fs 8 Fs 16 Fs Baseband Signal Images After the DAC Frequency Amplitude d Spectrum of Signal After Analog Filters Fs 8 Fs 16 Fs Baseband Signal Frequency ...

Page 81: ... of the DAC however has a large amount of quantization noise at higher frequencies and as described in the Anti Image Filtering section some images still remain near multiples of eight times the sample rate Two analog filters eliminate the quantization noise and the images The first is a fifth order switched capacitor filter in which the cutoff frequency scales with the sample frequency and is app...

Page 82: ...e floor drops from about 92 dB below full scale to about 120 dB below full scale Upon receiving any nonzero data the DAC instantly reverts to normal mode Mute mode is designed to quiet the background noise to extremely low levels when no waveforms are being generated Mute mode has a slightly different offset from the normal offset when zeros are being sent As a result the DAC has one offset for th...

Page 83: ...curacy Note Be sure to keep the cover on your computer to maintain forced air cooling Analog Input Channel Characteristics Number of channels Resolution 16 bits Type of ADC Delta sigma 128 times oversampling Sample rates Device Number of Channels Input Configuration 4451 2 Simultaneously sampled true differential 4452 4 4453 2 Single ended 4454 4 Device Sample Rates 4451 5 kS s to 204 8 kS s in in...

Page 84: ... samples Data transfers DMA programmed I O interrupt Transfer Characteristics INL relative accuracy 2 LSB DNL 0 5 LSB typ 1 LSB max no missing codes Device Gain Full scale Range Peak Linear Log 4451 4452 0 1 20 dB 42 4 V 0 316 10 dB 31 6 V 1 0 dB 10 0 3 16 10 dB 3 16 V 10 20 dB 1 00 V 31 6 30 dB 0 316 V 100 40 dB 0 100 V 316 50 dB 0 0316 V 1000 60 dB 0 0100 V 4453 4454 1 0 dB 10 V ...

Page 85: ...h 50 pF to AIGND Flatness relative to 1 kHz 3 dB bandwidth 0 493 fs Input coupling AC or DC software selectable AC 3 dB cutoff frequency 3 4 Hz Device Gain Max Offset 4451 4452 20 dB 30 mV 10 dB 10 mV 0 dB 3 mV 10 dB 1 mV 20 dB 300 µV 30 40 50 60 dB 100 µV 4453 4454 0 dB 3 mV Device Gain Flatness 4451 4452 0 10 20 30 40 dB 0 1 dB 0 to 95 kHz 204 8 kS s DC coupling 20 10 50 60 dB 1 dB 0 to 95 kHz 0...

Page 86: ...d or certified to operate beyond 42 4 V Inputs protected ACH0 ACH1 ACH2 ACH3 Common mode rejection ratio CMRR Device Gain Common Mode Range 4451 4452 Gain 0 dB both and should remain within 12 V of AIGND Gain 0 dB both and should remain within 42 4 V of AIGND 4453 4454 Gain 0 dB should remain within 12 V of AIGND Device Gain CMRR 4451 4452 0 dB 90 dB 0 dB 60 dB 4453 4454 0 dB 90 dB ...

Page 87: ... only at Gain 50 dB or 60 dB PCI 4453 4454 Idle channel noise 90 dBFS Dynamic Characteristics Alias free bandwidth DC to 0 464 fs Alias rejection 80 dB 0 536 fs fin 63 464 fs Spurious free dynamic range 95 dB THD 80 dB 90 dB for fin 20 kHz or signal 1 Vrms 65 0 95 0 90 0 85 0 80 0 75 0 70 0 1 000 000 1 000 10 000 100 000 Noise dB Full Scale Sample Rate S s Gain 60 dB Gain 50 dB Gain 40 dB Gain All...

Page 88: ...ains same configuration for all input channels Signal delay 42 sample periods any sample rate time from when signal enters analog input to when digital data is available Onboard Calibration Reference DC level 5 000 V 2 5 mV Temperature coefficient 5 ppm C max Long term stability 15 ppm Device Gain Phase Linearity 4451 4452 0 dB 1 0 dB 2 4453 4454 0 dB 1 Device Gain Interchannel Phase 4451 4452 0 d...

Page 89: ...16 bits Type of DAC Delta sigma 64 times oversampling Sample rates 1 25 to 51 2 kS s in increments of 47 684 µS s Frequency accuracy 25 ppm Output signal range software selectable for PCI 4451 FIFO buffer size 512 samples Data transfers DMA programmed I O Interrupt Transfer Characteristics Offset residual DC 5 mV max any gain Gain amplitude accuracy 0 1 dB fout 1 kHz Device Attenuation Full scale ...

Page 90: ... and may be shorted together indefinitely PCI 4453 yes output may be shorted to AO_SHLD or ground indefinitely Outputs protected PCI 4451 DAC0OUT DAC1OUT PCI 4453 DAC0OUT DAC1OUT Idle channel noise 91 dBFS DC to 23 kHz measurement bandwidth Dynamic Characteristics Image free bandwidth DC to 0 450 fs Image rejection 90 dB 0 550 fs fout 63 450 fs Spurious free dynamic range 90 dB DC to 100 kHz measu...

Page 91: ...to when analog signal appears at output terminals Digital I O PCI 4451 4452 Only Number of channels 8 input output Compatibility TTL CMOS Digital logic levels Power on state Input high impedance Data transfers Programmed I O Timing I O Number of channels 2 up down counter timers 1 frequency scaler Resolution Counter timers 24 bits Frequency scaler 4 bits Level Min Max Input low voltage Input high ...

Page 92: ...z Min source pulse duration 10 ns edge detect mode Min gate pulse duration 10 ns edge detect mode Data transfers DMA interrupts programmed I O DMA modes Scatter gather Triggers Analog Trigger Source PCI 4451 4453 ACH 0 1 PCI 4452 4454 ACH 0 3 Level full scale Slope Positive or negative software selectable Resolution 16 bits Hysteresis Programmable Digital Trigger Compatibility TTL Response Rising ...

Page 93: ...ector 4 65 to 5 25 VDC at 1 0 A Digital I O connector 4 65 to 5 25 VDC at 1 0 A PCI 4452 Requirements 5 V 2 2 A idle 2 5 A active 12 V 150 mA typical not including momentary relay switching 12 V unused 3 3 V unused Available power Analog I O connector 4 65 to 5 25 VDC at 1 0 A Digital I O connector 4 65 to 5 25 VDC at 1 0 A PCI 4453 Requirements 5 V 850 mA idle 1 0 A active 12 V 100 mA typical not...

Page 94: ...4 65 to 5 25 VDC at 1 0 A Physical Dimensions not including connectors 10 65 by 31 19 by 1 84 cm 4 19 by 12 28 by 0 73 in Analog I O connector 68 pin VHDCI female type PCI 4451 4452 Digital I O connector 50 pin VHDCI female type PCI 4453 4454 Digital trigger connector SMB female type Environment Operating temperature 0 C to 40 C Storage temperature range 25 C to 85 C Relative humidity 10 to 95 no ...

Page 95: ...al SHC68 DB25 cable It also illustrates the pin connections for the optional 68 pin digital accessories for the PCI 4451 and PCI 4452 devices Figure B 1 DB 25 Pinout for the SHC68 DB25 Cable 5 V GND DAC1OUT GND DAC0OUT NC ACH3 GND ACH2 NC ACH1 GND ACH0 13 12 11 10 9 8 7 6 5 4 3 2 1 GND DAC1OUT GND DAC0OUT NC ACH3 GND ACH2 NC ACH1 GND ACH0 25 24 23 22 21 20 19 18 17 16 15 14 ...

Page 96: ... GPCTR1_SOURCE GPCTR1_OUT PFI4 GPCTR1_GATE PFI7 PFI6 WFTRIG UPDATE PFI8 GPCTR0_SOURCE GPCTR0_OUT PFI9 GPCTR0_GATE FREQ_OUT DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND 5 V DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND 1 35 2 36 3 37 4 38 5 39 6 40 7 41 8 42 9 43 10 44 11 45 12 46 13 47 14 48 15 49 16 50 17 51 18 52 19 53 20 ...

Page 97: ...uestions FAQs and their corresponding answers or solutions including special sections devoted to our newest products The database is updated daily in response to new customer experiences and feedback Troubleshooting Wizards Step by step guides lead you through common problems and answer questions about our entire product line Wizards include screen shots that illustrate the steps being described a...

Page 98: ...ide information on local services You can access these Web sites from www ni com worldwide If you have trouble connecting to our Web site please contact your local National Instruments office or the source from which you purchased your National Instruments product s to obtain support For telephone support in the United States dial 512 795 8248 For telephone support outside the United States contac...

Page 99: ...lue p pico 10 12 n nano 10 9 µ micro 10 6 m milli 10 3 k kilo 103 M mega 106 G giga 109 Numbers Symbols degree Ω ohm percent positive of or plus negative of or minus per A A amperes AC alternating current AC coupled allowing the transmission of AC signals while blocking DC signals A D analog to digital ...

Page 100: ...uracy in the resulting digitized signal and reduces noise amplitude flatness a measure of how close to constant the gain of a circuit remains over a range of frequencies AO Start Trigger LabVIEW name for WFTRIG See WFTRIG AO Update LabVIEW name for UPDATE See UPDATE asynchronous 1 hardware a property of an event that occurs at an arbitrary time without synchronization to a reference clock 2 softwa...

Page 101: ...rs when an input signal exceeds the input range of the amplifier clock hardware component that controls timing for reading from or writing to groups CMOS complementary metal oxide semiconductor CMRR common mode rejection ratio a measure of an instrument s ability to reject interference from a common mode signal usually expressed in decibels dB code width the smallest detectable change in an input ...

Page 102: ...ent a digital or analog output channel is capable of sourcing or sinking while still operating within voltage range specifications current sinking the ability of a DAQ device to dissipate current for analog or digital output signals current sourcing the ability of a DAQ device to supply current for analog or digital output signals D D A digital to analog DAC digital to analog converter an electron...

Page 103: ...sigma modulating ADC a high accuracy circuit that samples at a higher rate and lower resolution than is needed and by means of feedback loops pushes the quantization noise above the frequency range of interest This out of band noise is typically removed by digital filters device a plug in data acquisition device card or pad that can contain multiple channels and devices Plug in boards PCMCIA cards...

Page 104: ...nal drivers software that controls a specific hardware device such as a DAQ device or a GPIB interface device DSA dynamic signal acquisition dynamic range the ratio of the largest signal level a circuit can handle to the smallest signal level it can handle usually taken to be the noise level normally expressed in decibels E EEPROM electrically erasable programmable read only memory ROM that can be...

Page 105: ... the effect of latencies associated with getting the data from system memory to the DAQ device filtering a type of signal conditioning that allows you to attenuate unwanted portions of the signal you are trying to measure fin input signal frequency FIR finite impulse response a non recursive digital filter with linear phase flash ADC an ADC whose output code is determined in a single step by a ban...

Page 106: ...isition and gather data at a known position in time relative to a trigger signal high impedance in logic circuits designed to have three possible states 0 1 and hi Z the hi Z high impedance state effectively removes the output from its circuit and can be used to simplify bus communication by wire ANDing tri state inputs Hz hertz cycles per second Specifically refers to the repetition frequency of ...

Page 107: ...e with respect to ground is proportional to the difference between the voltages at its two inputs interrupt a computer signal indicating that the CPU should suspend its current task to service a designated activity I O input output the transfer of data to from a computer system involving communications channels operator interface devices and or data acquisition and control interfaces IOH current o...

Page 108: ...nse to the equation R KS where R response S stimulus and K a constant linearization a type of signal conditioning in which software linearizes the voltage levels from transducers so the voltages can be scaled to measure physical phenomena LSB least significant bit M memory buffer See buffer MS million samples MSB most significant bit N NC normally closed or not connected NI DAQ National Instrument...

Page 109: ...onents higher than half the frequency at which it is sampled then the original signal can be recovered without distortion O offset binary format a method of digitally encoding sound that represents the range of amplitude values as an unsigned number with the midpoint of the range representing silence For example an 8 bit sound stored in offset binary format would contain sample values ranging from...

Page 110: ...onnection on a computer or a remote controller 2 a digital port consisting of four or eight lines of digital input and or output posttriggering the technique used on a DAQ device to acquire a programmed number of samples after trigger conditions are met ppm parts per million pretriggering the technique used on a DAQ device to keep a continuous buffer filled with data so that when the trigger condi...

Page 111: ...tude RSE See SE RTSI bus real time system integration bus the National Instruments timing bus that connects DAQ devices directly by means of connectors on top of the boards for precise synchronization of functions S s seconds S samples sample counter the clock that counts the output of the channel clock in other words the number of samples taken On devices with simultaneous sampling this counter c...

Page 112: ...require dip switches or jumpers to configure resources on the devices also called Plug and Play devices synchronous 1 hardware a property of an event that is synchronized to a reference clock 2 software a property of a function that begins an operation and returns only when the operation is complete system noise a measure of the amount of noise seen by an analog circuit or an ADC when the analog i...

Page 113: ...system for digitally encoding sound that stores the amplitude values as a signed number with silence represented by a sample with a value of 0 For example with 8 bit sound samples two s complement values would range from 128 to 127 with 0 meaning silence See offset binary format U undersampling sampling at a rate lower than the Nyquist frequency can cause aliasing update the output equivalent of a...

Page 114: ...f hardware and or software elements typically used with a PC that has the functionality of a classic stand alone instrument 2 a LabVIEW software module VI which consists of a front panel user interface and a block diagram program W waveform multiple voltage readings taken at a specific sampling rate WFTRIG trigger that initiates waveform generation ...

Page 115: ... 21 EXTSTROBE signal 4 21 to 4 22 PFI0 TRIG1 EXT_TRIG signal 4 20 PFI1 TRIG2 PRETRIG signal 4 21 typical posttriggered acquisition figure 4 19 typical pretriggered acquisition figure 4 20 ADC 6 9 to 6 10 AIGND signal analog input signal connections 4 12 to 4 13 analog I O pin assignments table 4 3 analog I O signal summary table 4 4 AI_SHLD 0 3 signal analog I O pin assignments table 4 6 analog I ...

Page 116: ...ge filtering 6 12 to 6 13 calibration 6 14 DAC 6 14 mute feature 6 15 analog power connections 4 16 analog trigger 3 8 to 3 12 above high level analog triggering mode figure 3 9 below low level analog triggering mode figure 3 9 high hysteresis analog triggering mode figure 3 10 inside region analog triggering mode figure 3 10 low hysteresis analog triggering mode figure 3 10 specifications A 10 an...

Page 117: ...connectors See I O connectors conventions used in manual xi xii CONVERT signal digital I O pin assignments table 4 9 digital I O signal summary table 4 11 timing connections 4 21 custom cables analog accessories 1 7 analog cables 1 6 digital cables 1 7 D DAC mute feature 6 15 signal spectra in DAC figure 6 13 theory of operation 6 14 DAC0OUT signal analog I O pin assignments table PCI 4451 4452 4 ...

Page 118: ...scriptions pin assignments table 4 9 to 4 10 pin connections figure 4 8 signal summary table 4 11 digital power connections 4 18 digital trigger specifications A 10 DIO 0 7 signal digital I O pin assignments table 4 9 digital I O signal connections 4 17 digital I O signal summary table 4 11 direct digital synthesis DDS technology 3 14 documentation conventions used in manual xi xii how to use manu...

Page 119: ...put 3 4 to 3 6 input mode 3 4 input polarity and range 3 4 to 3 6 input range selection considerations 3 5 to 3 6 analog output 3 6 to 3 8 analog trigger 3 8 to 3 12 block diagrams analog function 3 2 to 3 3 digital function 3 1 digital I O 3 12 to 3 13 timing signal routing 3 13 to 3 14 device and RTSI clocks 3 14 programmable function inputs 3 13 I input coupling analog input 3 4 theory of opera...

Page 120: ...o 1 5 unpacking 1 3 PFI0 TRIG1 EXT_TRIG signal digital I O pin assignments table 4 9 digital I O signal summary table 4 11 timing connections 4 20 PFI1 TRIG2 PRETRIG signal digital I O pin assignments table 4 9 digital I O signal summary table 4 11 timing connections 4 21 PFI3 GPCTR1_SOURCE signal digital I O pin assignments table 4 9 digital I O signal summary table 4 11 PFI4 GPCTR1_GATE signal d...

Page 121: ...nal summary table 4 11 RTSI bus signal connection figure 3 12 RTSI clocks 3 14 RTSI trigger lines overview 3 12 signal connection figure 3 12 S sample rate and device configuration 3 15 sample update clock frequency selecting 3 14 to 3 15 signal connections analog input 4 12 to 4 13 digital I O 4 17 field wiring considerations 4 28 to 4 29 I O connectors 4 1 to 4 11 68 pin digital connector pin co...

Page 122: ... A 12 power requirements A 11 to A 12 timing I O A 9 to A 10 T technical support resources C 1 to C 2 theory of operation See analog operation theory timing connections 4 18 to 4 28 acquisition timing connections 4 19 to 4 22 CONVERT signal 4 21 EXTSTROBE signal 4 21 to 4 22 PFI0 TRIG1 EXT_TRIG signal 4 20 PFI1 TRIG2 PRETRIG signal 4 21 typical posttriggered acquisition figure 4 19 typical pretrig...

Page 123: ...10 U unpacking PCI 445X 1 3 update clock frequency selecting 3 14 to 3 15 update rate and device configuration 3 15 UPDATE signal digital I O pin assignments table 4 10 digital I O signal summary table 4 11 timing connections 4 22 V VirtualBench software 1 4 voltage output specifications A 8 W waveform generation timing connections 4 22 UPDATE signal 4 22 WFTRIG signal 4 22 Web support from Nation...

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