Chapter 4
Signal Connections
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National Instruments Corporation
4-19
PCI-4451/4452/4453/4454 User Manual
Programmable Function Input Connections (PCI-4451/4452 Only)
You can individually enable each of the PFI pins to output a specific
internal timing signal. For example, if you need the GPCTR1_SOURCE
signal as an output on the I/O connector, software can turn on the output
driver for the PFI3/GPCTR1_SOURCE pin.
Caution
Be careful not to drive a PFI signal externally when it is configured as an output.
As an input, you can individually configure each PFI for edge or level
detection and for polarity selection as well. You can use the polarity
selection for any of the timing signals, but your choice of edge or level
detection depends on the particular timing signal you are controlling. The
detection requirements for each timing signal are listed within the section
that discusses that individual signal.
In edge-detection mode, the minimum pulse width required is 10 ns. This
applies for both rising-edge and falling-edge polarity settings. There is no
maximum pulse-width requirement in edge-detect mode.
In level-detection mode, there are no minimum or maximum pulse-width
requirements imposed by the PFIs themselves, but there can be limits
imposed by the particular timing signal you are controlling. These
requirements are listed in this chapter.
Acquisition Timing Connections
The acquisition timing signals are PFI0/TRIG1, PFI1/TRIG2,
CONVERT*, and EXTSTROBE*. EXTSTROBE* is used only on the
PCI-4451/4452.
Posttriggered data acquisition allows you to view only data that you acquire
after receiving a trigger event. A typical posttriggered acquisition sequence
is shown in Figure 4-9.
Figure 4-9.
Typical Posttriggered Acquisition
1
3
0
4
2
TRIG1
CONVERT*
Scan Counter
