Chapter 3 Hardware Overview
PCI-4451/4452/4453/4454 User Manual 3-14 www.ni.com
Device and RTSI Clocks
A PCI-445X can use either its internal 20 MHz timebase or a timebase
received over the RTSI bus. In addition, if you configure the device to use
the internal timebase, you can program the device to drive its internal
timebase over the RTSI bus to another device that you program to receive
this timebase signal. The default configuration at startup is to use the
internal timebase without driving the RTSI bus timebase signal. This
timebase is software-selectable. You cannot use these signals for the
generating of sample rates or update rates. Refer to the Selecting
Sample/Update Clock Frequency section for information on sample/update
clock generation.
Selecting Sample/Update Clock Frequency
The two analog input channels of the PCI-4451 and the four analog input
channels of the PCI-4452 are simultaneously sampled at any
software-programmable rate from 5.0 kS/s to 204.8 kS/s in 190.7
µ
S/s
increments (worst case). The two analog input channels of the PCI-4453
and the four input channels of the PCI-4454 are simultaneously sampled at
any software-programmable rate from 5.0 kS/s to 51.2 kS/s in 47.684 µS/s
increments (worst case). The devices use direct digital synthesis (DDS)
technology so that you can choose the correct sample rate required for your
application. All the input channels acquire data at the same rate. One input
channel cannot acquire data at a different rate from another input channel.
♦
PCI-4451/4453
The two analog output channels of the PCI-4451/4453 are updated
simultaneously at any software programmable rate from 1.25 kS/s to
51.2 kS/s in 47.684
µ
S/s increments (worst case). The input sample rate
and output update rate on the PCI-4451/4453 are synchronized and derived
from the same DDS clock. The input and output clocks can differ from each
other by a factor of 2 (1, 2, 4, 8, …, 128) while still maintaining their
synchronization as long as the lower bounds for update and sample rate are
maintained. All the output channels update data at the same rate. One
output channel cannot update data at a different rate from another output
channel.
