Chapter 6
Digital I/O
©
National Instruments
6-17
X Series User Manual
DO Sample Clock Signal
The device
u
ses the DO Sample Clock (do/SampleClock) signal to
u
pdate
the DO terminals with the next sample from the DO waveform generation
FIFO.
Yo
u
can specify an internal or external so
u
rce for DO Sample Clock. Yo
u
can also specify whether the DAC
u
pdate begins on the rising edge or
falling edge of DO Sample Clock. If the DAQ device receives a DO Sample
Clock when the FIFO is empty, the DAQ device reports an
u
nderflow error
to the host software.
Using an Internal Source
One of the following internal signals can drive DO Sample Clock:
•
DI Sample Clock (di/SampleClock)
•
DO Sample Clock (do/SampleClock)
•
AI Sample Clock (ai/SampleClock)
•
AI Convert Clock (ai/ConvertClock)
•
AO Sample Clock (ao/SampleClock)
•
Co
u
nter
n
Sample Clock
•
Co
u
nter
n
Internal O
u
tp
u
t
•
Freq
u
ency O
u
tp
u
t
•
DI Change Detection o
u
tp
u
t
Several other internal signals can be ro
u
ted to DO Sample Clock thro
u
gh
internal ro
u
tes. Refer to
Device Routing in MAX
in the
NI-DAQmx Help
or
the
LabVIEW Help
for more information.
Using an External Source
Use one of the following external signals as the so
u
rce of DO Sample
Clock:
•
PFI <0..15>
•
RTSI <0..7>
•
PXI_STAR
•
PXIe-DSTAR<A,B>
•
Analog Comparison Event (an analog trigger)
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