Chapter 4
Connecting Signals
©
National Instruments Corporation
4-49
leave the DIO7 pin free for general use. Figure 4-37 shows the timing
requirements for the GATE and SOURCE input signals and the timing
specifications for the OUT output signals of the AT E Series device.
Figure 4-37.
GPCTR Timing Summary
The GATE and OUT signal transitions shown in Figure 4-37 are referenced
to the rising edge of the SOURCE signal. This timing diagram assumes that
the counters are programmed to count rising edges. The same timing
diagram, but with the source signal inverted and referenced to the falling
edge of the source signal, would apply when the counter is programmed to
count falling edges.
The GATE input timing parameters are referenced to the signal at the
SOURCE input or to one of the internally generated signals on the
AT E Series device. Figure 4-37 shows the GATE signal referenced to
the rising edge of a source signal. The gate must be valid (either high or
low) for at least 10 ns before the rising or falling edge of a source signal
for the gate to take effect at that source edge, as shown by t
gsu
and t
gh
in
Figure 4-37. The gate signal is not required to be held after the active edge
of the source signal.
t
sc
t
sc
t
sp
t
sp
t
sp
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
t
gsu
t
gsu
t
gh
t
gh
t
gw
t
gw
t
out
t
out
Source Clock Period
Source Pulse Width
Gate Setup Time
Gate Hold Time
Gate Pulse Width
Output Delay Time
50 ns minimum
23 ns minimum
10 ns minimum
0 ns minimum
10 ns minimum
80 ns maximum
SOURCE
GATE
OUT
