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Chapter 4

Connecting Signals

AT E Series User Manual

4-24

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Single-Ended Connection Considerations

A single-ended connection is one in which the AT E Series device AI
signal is referenced to a ground that can be shared with other input signals.
The input signal is tied to the positive input of the PGIA, and the ground is
tied to the negative input of the PGIA.

When every channel is configured for single-ended input, up to 16 analog
input channels are available (up to 64 channels on the AT-MIO-64E-3).

You can use single-ended input connections for any input signal that meets
the following conditions:

•

The input signal is high level (greater than 1 V).

•

The leads connecting the signal to the AT E Series device are less than
10 ft (3 m).

•

The input signal can share a common reference point with other
signals.

DIFF input connections are recommended for greater signal integrity for
any input signal that does not meet the preceding conditions.

You can software configure the AT E Series device channels for two
different types of single-ended connections—RSE configuration and
NRSE configuration. The RSE configuration is used for floating signal
sources; in this case, the AT E Series device provides the reference ground
point for the external signal. The NRSE input configuration is used for
ground-referenced signal sources; in this case, the external signal supplies
its own reference ground point and the AT E Series device should not
supply one.

In single-ended configurations, more electrostatic and magnetic noise
couples into the signal connections than in differential configurations. The
coupling is the result of differences in the signal path. Magnetic coupling is
proportional to the area between the two signal conductors. Electrical
coupling is a function of how much the electric field differs between the
two conductors.

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Summary of Contents for AT E Series

Page 1: ...DAQ AT E Series User Manual Multifunction I O Devices for the PC AT AT E Series User Manual May 2002 Edition Part Number 370507A 01 ...

Page 2: ...1 France 01 48 14 24 24 Germany 089 741 31 30 Greece 30 1 42 96 427 Hong Kong 2645 3186 India 91 80 4190000 Israel 03 6393737 Italy 02 413091 Japan 03 5472 2970 Korea 02 3451 3400 Malaysia 603 9596711 Mexico 001 800 010 0793 Netherlands 0348 433466 New Zealand 09 914 0488 Norway 32 27 73 00 Poland 0 22 3390 150 Portugal 351 210 311 210 Russia 095 238 7139 Singapore 6 2265886 Slovenia 386 3 425 420...

Page 3: ...ntenance instructions owner s modification of the product owner s abuse misuse or negligent acts and power failure or surges fire flood accident actions of third parties or other events outside reasonable control Copyright Under the copyright laws this publication may not be reproduced or transmitted in any form electronic or mechanical including photocopying recording storing in an information re...

Page 4: ...uments could void the user s authority to operate the equipment under the FCC Rules Class A Federal Communications Commission This equipment has been tested and found to comply with the limits for a Class A digital device pursuant to part 15 of the FCC Rules These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial enviro...

Page 5: ...bought for OEMs if also available from an original manufacturer that also markets in the EU or where compliance is not required as for electrically benign apparatus or cables To obtain the DoC for this product click Declaration of Conformity at ni com hardref nsf This Web site lists the DoCs by product family Select the appropriate product family followed by your product and a link to the DoC appe...

Page 6: ...gister Level Programming 1 4 Optional Equipment 1 5 Custom Cabling 1 5 Unpacking 1 6 Safety Information 1 6 Chapter 2 Installing and Configuring the Device Installing the Software 2 1 Installing the Hardware 2 1 Configuring the Device 2 2 Bus Interface 2 2 Plug and Play 2 2 Switchless Data Acquisition 2 3 Base I O Address Selection 2 3 DMA Channel Selection 2 3 Interrupt Channel Selection 2 3 Chap...

Page 7: ... Sources 4 17 Input Configurations 4 18 Differential Connection Considerations DIFF Input Configuration 4 20 Differential Connections for Ground Referenced Signal Sources 4 21 Differential Connections for Nonreferenced or Floating Signal Sources 4 22 Single Ended Connection Considerations 4 24 Single Ended Connections for Floating Signal Sources RSE Configuration 4 25 Single Ended Connections for ...

Page 8: ...R0_UP_DOWN Signal 4 46 GPCTR1_SOURCE Signal 4 47 GPCTR1_GATE Signal 4 47 GPCTR1_OUT Signal 4 48 GPCTR1_UP_DOWN Signal 4 48 FREQ_OUT Signal 4 50 Timing Specifications for Digital I O Ports A B and C 4 50 Mode 1 Input Timing 4 52 Mode 1 Output Timing 4 53 Mode 2 Bidirectional Timing 4 54 Field Wiring Considerations 4 55 Chapter 5 Calibrating the Device Loading Calibration Constants 5 1 Self Calibrat...

Page 9: ...Contents AT E Series User Manual x ni com Appendix D Technical Support and Professional Services Glossary Index ...

Page 10: ...s for the PC AT series computers Supported functions include analog input AI analog output AO digital I O DIO and timing I O TIO Conventions The following conventions appear in this manual Angle brackets that contain numbers separated by an ellipsis represent a range of values associated with a bit or signal name for example DIO 3 0 The symbol indicates that the following text applies only to a sp...

Page 11: ...e manuals you have as follows Getting Started with SCXI If you are using SCXI this is the first manual you should read It gives an overview of the SCXI system and contains the most commonly needed information for the modules chassis and software The SCXI hardware user manuals If you are using SCXI read these manuals next for detailed information about signal connections and module configuration Th...

Page 12: ...f you are using accessory products read the terminal block and cable assembly installation guides They explain how to physically connect the relevant pieces of the system Consult these guides when you are making the connections Related Documentation The following documents contain information that you might find helpful as you read this manual AT E Series Register Level Programmer Manual DAQ STC T...

Page 13: ...evices This feature is made possible by the National Instruments DAQ PnP bus interface chip that connects the device to the AT I O bus The DAQ PnP implements the Plug and Play ISA Specification so that the DMA interrupts and base I O addresses are all software configurable This allows you to easily change the AT E Series device configuration without having to remove the device from the computer Th...

Page 14: ...rumentation front end for plug in DAQ devices Detailed specifications of the AT E Series devices are in Appendix A Specifications What You Need to Get Started To set up and use the AT E Series device you need the following One of the following devices AT MIO 16E 1 NI 6070E for ISA AT MIO 16E 2 NI 6060E for ISA AT MIO 64E 3 NI 6061E for ISA AT MIO 16E 10 NI 6020E for ISA AT MIO 16DE 10 NI 6021E for...

Page 15: ...any of the complex interactions such as programming interrupts between the computer and the DAQ hardware NI DAQ maintains a consistent software interface among its different versions so that you can change platforms with minimal modifications to the code Whether you are using LabVIEW Measurement Studio or other ADEs your application uses NI DAQ as illustrated in Figure 1 1 Figure 1 1 The Relations...

Page 16: ...ts DAQ hardware These ActiveX controls provide a high level programming interface for building virtual instruments For Visual C developers Measurement Studio offers a set of Visual C classes and tools to integrate those classes into Visual C applications The libraries ActiveX controls and classes are available with Measurement Studio and NI DAQ Using LabVIEW or Measurement Studio greatly reduces t...

Page 17: ...ays For more specific information about these products refer to ni com catalog or call the office nearest you Custom Cabling National Instruments offers cables and accessories for you to prototype your application or to use if you frequently change device interconnections If you want to develop your own cable however the following guidelines may be useful For the AI signals shielded twisted pair w...

Page 18: ...ty Information The following section contains important safety information that you must follow during installation and use of the product Do not operate the product in a manner not specified in this document Misuse of the product can result in a hazard You can compromise the safety protection built into the product if the product is damaged in any way If the product is damaged return it to NI for...

Page 19: ...is rated Do not exceed the maximum ratings for the product Remove power from signal lines before connection to or disconnection from the product Operate this product only at or below the installation category stated in Appendix A Specifications The following is a description of installation categories Installation Category I is for measurements performed on circuits not directly connected to MAINS...

Page 20: ... Other examples of Installation Category III are wiring including cables bus bars junction boxes switches socket outlets in the building fixed installation and equipment for industrial use such as stationary motors with a permanent connection to the building fixed installation Installation Category IV is for measurements performed at the source of the low voltage 1 000 V installation Examples of I...

Page 21: ...etected Installing the Hardware You can install an AT E Series device in any available expansion slot in the PC However to achieve best noise performance you should leave as much room as possible between the AT E Series device and other devices and hardware The following are general installation instructions but consult the PC user manual or technical reference manual for specific instructions and...

Page 22: ...ition related configuration explained in Chapter 3 Hardware Overview includes such settings as AI polarity and range AO reference source and other settings For more information about data acquisition related configuration refer to the NI DAQ user manual Bus Interface The AT E Series devices work in either a Plug and Play mode or a switchless mode These modes dictate how the base I O address DMA ch...

Page 23: ...e of 20 to FFE0 hex Each AT E Series device occupies 32 bytes of address space and must be located on a 32 byte boundary Therefore valid addresses include 100 120 140 3C0 3E0 hex This selection is software configured and does not require you to manually change any settings on the device DMA Channel Selection The AT E Series devices can achieve high transfer rates by using up to three 16 bit DMA ch...

Page 24: ... 24 default 218 to 21F 220 to 23F Previous generation of AT MIO devices default 240 to 25F AT DIO 32F default 260 to 27F Lab PC PC default 278 to 28F AT Parallel Printer Port 2 LPT2 279 Reserved for Plug and Play operation 280 to 29F WD EtherCard default 2A0 to 2BF 2E2 to 2F7 2F8 to 2FF PC AT Serial Port 2 COM2 300 to 30F 3Com EtherLink default 310 to 31F 320 to 32F ICM PC XT Fixed Disk Controller...

Page 25: ...rinter Adapter 0 3C0 to 3CF Enhanced Graphics Adapter VGA 3D0 to 3DF Color Graphics Monitor Adapter VGA 3E0 to 3EF 3F0 to 3F7 Diskette Controller 3F8 to 3FF Serial Port 1 COM1 A79 Reserved for Plug and Play operation Table 2 2 PC AT Interrupt Assignment Map IRQ Device 15 Available 14 Fixed Disk Controller 13 Coprocessor 12 AT DIO 32F default 11 AT DIO 32F default 10 AT MIO 16 default 9 PC Network ...

Page 26: ...BSC BSC Alternate 3 Serial Port 2 COM2 BSC BSC Alternate Cluster primary PC Network PC Network Alternate WD EtherCard default 3Com EtherLink default 2 IRQ 8 15 Chain from interrupt controller 2 1 Keyboard Controller Output Buffer Full 0 Timer Channel 0 Output Table 2 3 PC AT 16 bit DMA Channel Assignment Map Channel Device 7 AT MIO 16 series default 6 AT MIO 16 series default AT DIO 32F default 5 ...

Page 27: ...tion Memory NI PGIA Gain Amplifier Calibration Mux Mux Mode Selection Switches Analog Muxes Voltage REF Calibration DACs Dither Circuitry Trigger Analog Trigger Circuitry 2 Trigger Level DACs 6 Calibration DACs DAC0 DAC1 3 DAQ STC Analog Input Timing Control Analog Output Timing Control Digital I O Trigger Counter Timing I O RTSI Bus Interface DMA Interrupt Request Bus Interface 8 8 DAC FIFO 8 Dat...

Page 28: ...Switches Analog Muxes Voltage REF Calibration DACs Dither Circuitry Trigger Analog Trigger Circuitry 2 Trigger Level DACs 6 Calibration DACs DAC0 DAC1 3 DAQ STC Analog Input Timing Control Analog Output Timing Control Digital I O Trigger Counter Timing I O RTSI Bus Interface DMA Interrupt Request Bus Interface 32 32 DAC FIFO 8 Data 16 AI Control Data 16 Analog Input Control EEPROM Control DMA Inte...

Page 29: ...8 12 Bit Sampling A D Converter EEPROM Configuration Memory NI PGIA Gain Amplifier Calibration Mux Mux Mode Selection Switches Analog Muxes Voltage REF Calibration DACs Dither Circuitry 6 Calibration DACs DAC0 DAC1 3 DAQ STC Analog Input Timing Control Analog Output Timing Control Digital I O Trigger Counter Timing I O RTSI Bus Interface DMA Interrupt Request Bus Interface 8 8 8255 DIO Port 8 AI C...

Page 30: ...x Mux Mode Selection Switches Analog Muxes Voltage REF Calibration DACs 4 Calibration DACs DAC0 DAC1 7 DAQ STC Analog Input Timing Control Analog Output Timing Control Digital I O Trigger Counter Timing I O RTSI Bus Interface DMA Interrupt Request Bus Interface 8 8 8 AI Control Analog Input Control EEPROM Control DMA Interface DAQ PnP DAQ STC Bus Interface Plug and Play Analog Output Control 8255 ...

Page 31: ...ammable Gain Amplifier Calibration Mux Mux Mode Selection Switches Analog Muxes Voltage REF Calibration DACs 7 DAQ STC Analog Input Timing Control Analog Output Timing Control Digital I O Trigger Counter Timing I O RTSI Bus Interface DMA Interrupt Request Bus Interface 8 8 8 AI Control Analog Input Control EEPROM Control DMA Interface DAQ PnP DAQ STC Bus Interface Plug and Play Analog Output Contr...

Page 32: ...4E 3 The DIFF input configuration uses up to eight channels 32 channels on the AT MIO 64E 3 Input modes are programmed on a per channel basis for multimode scanning For example you can configure the circuitry to scan Timing PFI Trigger I O Connector 3 2 RTSI Bus AT I O Channel Digital I O 8 16 Bit Sampling A D Converter EEPROM Configuration Memory Programmable Gain Amplifier Calibration Mux Mux Mo...

Page 33: ...olar input range of 10 V 0 to 10 V and a bipolar input range of 10 V 5 V You can program polarity and range settings on a per channel basis so that you can configure each input channel uniquely The software programmable gain on these devices increases their overall flexibility by matching the input signal ranges to those that the ADC can accommodate The AT MIO 16E 1 AT MIO 16E 2 AT MIO 64E 3 Table...

Page 34: ...0 and AT MIO 16XE 50 have a unipolar input range of 10 V 0 to 10 V and a bipolar input range of 20 V 10 V You can program polarity and range settings on a per channel basis so that you can configure each input channel uniquely Table 3 2 Actual Range and Measurement Precision Range Configuration Gain Actual Input Range Precision1 0 to 10 V 1 0 2 0 5 0 10 0 20 0 50 0 100 0 0 to 10 V 0 to 5 V 0 to 2 ...

Page 35: ...gain setting you can use the full resolution of the ADC to measure the input signal Table 3 3 shows the overall input range and precision according to the input range configuration and gain used Table 3 3 Actual Range and Measurement Precision for the AT MIO 16XE 10 AT AI 16XE 10 and AT MIO 16XE 50 Range Configuration Gain Actual Input Range Precision1 0 to 10 V 1 02 2 02 5 02 10 02 20 02 50 02 10...

Page 36: ...pplications noise modulation is decreased and differential linearity is improved by the addition of the dither When taking DC measurements such as when checking the device calibration you should enable dither and average about 1 000 points to take a single reading This process removes the effects of quantization and reduces measurement noise resulting in improved resolution For high speed applicat...

Page 37: ... the AT E Series devices is independent of the selected gain even at the maximum sampling rate The settling time for the high channel count and very high speed devices is gain dependent which can affect the useful sampling rate for a given gain No extra settling time is necessary between channels as long as the gain is constant and source impedances are low Refer to Appendix A Specifications for a...

Page 38: ...ull scale range on channel 1 the input circuitry has to settle within 0 00004 0 4 ppm or 1 400 LSB of the 4 V step It may take as long as 200 µs for the circuitry to settle this much In general this extra settling time is not needed when the PGIA is switching to a lower gain Settling times can also increase when scanning high impedance signals due to a phenomenon called charge injection where the ...

Page 39: ...ference Selection AT MIO 16E 1 AT MIO 16E 2 AT MIO 64E 3 AT MIO 16E 10 and AT MIO 16DE 10 only You can connect each D A converter DAC to the AT E Series device internal reference of 10 V or to the external reference signal connected to the external reference EXTREF pin on the I O connector This signal applied to EXTREF should be between 10 and 10 V You do not need to configure both channels for th...

Page 40: ...16E 2 and AT MIO 64E 3 contains a reglitch circuit that generates uniform glitch energy at every code rather than large glitches at the major code transitions This uniform glitch energy appears as a multiple of the update rate in the frequency spectrum Notice that this reglitch circuit does not eliminate the glitches it only makes them more uniform in size Reglitching is normally disabled at start...

Page 41: ...lt in false triggering when the pin is left unconnected To avoid false triggering make sure this pin is connected to a low impedance signal source less than 10 kΩ source impedance if you plan to enable this input using software Figure 3 8 Analog Trigger Block Diagram There are five analog triggering modes available as shown in Figures 3 9 through 3 13 You can set lowValue and highValue independent...

Page 42: ...is generated when the signal value is greater than highValue LowValue is unused Figure 3 10 Above High Level Analog Triggering Mode In inside region analog triggering mode the trigger is generated when the signal value is between the lowValue and the highValue Figure 3 11 Inside Region Analog Triggering Mode lowValue Trigger highValue Trigger highValue Trigger lowValue ...

Page 43: ...specified by highValue Figure 3 13 Low Hysteresis Analog Triggering Mode The analog trigger circuit generates an internal digital trigger based on the AI signal and the user defined trigger levels This digital trigger can be used by any of the timing sections of the DAQ STC including the AI AO and general purpose counter timer sections For example the AI section can be configured to acquire n scan...

Page 44: ...ters The up down control signals are input only and do not affect the operation of the DIO lines Timing Signal Routing The DAQ STC provides a very flexible interface for connecting timing signals to other devices or external circuitry The AT E Series device uses the RTSI bus for interconnecting timing signals between devices and the Programmable Function Input PFI pins on the I O connector for con...

Page 45: ...es including the external signals RTSI 0 6 and PFI 0 9 and the internal signals Sample Interval Counter TC and GPCTR0_OUT Many of these timing signals are also available as outputs on the RTSI pins as indicated in the RTSI Triggers section later in this chapter and on the PFI pins as indicated in Chapter 4 Connecting Signals RTSI Trigger 0 6 PFI 0 9 CONVERT Sample Interval Counter TC GPCTR0_OUT ...

Page 46: ... Clocks Many functions performed by the AT E Series devices require a frequency timebase to generate the necessary timing signals for controlling A D conversions DAC updates or general purpose signals at the I O connector An AT E Series device can use either its internal 20 MHz timebase or a timebase received over the RTSI bus In addition if you configure the device to use the internal timebase yo...

Page 47: ...fer to the Timing Connections section of Chapter 4 Connecting Signals for a description of the signals shown in Figure 3 15 RTSI Bus Connector Switch RTSI Switch Clock Trigger 7 UPDATE WFTRIG GPCTR0_SOURCE GPCTR0_GATE GPCTR0_OUT UISOURCE GPCTR1_SOURCE GPCTR1_GATE RTSI_OSC 20 MHz DAQ STC TRIG1 TRIG2 CONVERT STARTSCAN AIGATE SISOURCE ...

Page 48: ...4 3 shows the pin assignments for the 100 pin I O connector on the AT MIO 16DE 10 Refer to Appendix B Optional Cable Connector Descriptions for the pin assignments for the 50 pin connectors A signal description follows the connector pinouts Caution Connections that exceed any of the maximum ratings of input or output signals on the AT E Series devices can damage the AT E Series device and the PC M...

Page 49: ...FI0 TRIG1 DGND DGND 5V DGND DIO6 DIO1 DGND DIO4 EXTREF2 DAC1OUT 1 DAC0OUT 1 ACH15 AIGND ACH6 ACH13 AIGND ACH4 AIGND ACH3 ACH10 AIGND ACH1 ACH8 DGND PFI8 GPCTR0_SOURCE PFI7 STARTSCAN GPCTR1_OUT PFI4 GPCTR1_GATE PFI3 GPCTR1_SOURCE PFI2 CONVERT DGND DGND DGND EXTSTROBE SCANCLK DIO3 DIO7 DIO2 DGND DIO5 DIO0 DGND AOGND AOGND AIGND ACH7 ACH14 AIGND ACH5 ACH12 AISENSE ACH11 AIGND ACH2 ACH9 AIGND ACH0 1 3...

Page 50: ..._OUT ACH55 PFI9 GPCTR0_GATE ACH62 PFI8 GPCTR0_SOURCE ACH54 PFI7 STARTSCAN ACH61 PFI6 WFTRIG ACH53 PFI5 UPDATE ACH60 GPCTR1_OUT ACH52 PFI4 GPCTR1_GATE ACH59 PFI3 GPCTR1_SOURCE ACH51 PFI2 CONVERT ACH58 PFI1 TRIG2 ACH50 FI0 TRIG1 ACH57 EXTSTROBE ACH49 SCANCLK ACH56 5V ACH48 5V ACH47 DGND ACH39 DIO7 ACH46 DIO3 ACH38 DIO6 ACH45 DIO2 ACH37 DIO5 ACH44 DIO1 ACH36 DIO4 AIGND DIO0 AISENSE2 DGND ACH43 AOGND ...

Page 51: ...54 3 53 2 52 1 51 FREQ_OUT GND GPCTR0_OUT 5V PFI9 GPCTR0_GATE GND PFI8 GPCTR0_SOURCE PA0 PFI7 STARTSCAN GND PFI6 WFTRIG PA1 PFI5 UPDATE GND GPCTR1_OUT PA2 PFI4 GPCTR1_GATE GND PFI3 GPCTR1_SOURCE PA3 PFI2 CONVERT GND PFI1 TRIG2 PA4 PFI0 TRIG1 GND EXTSTROBE PA5 SCANCLK GND 5V PA6 5V GND DGND PA7 DIO7 GND DIO3 PB0 DIO6 GND DIO2 PB1 DIO5 GND DIO1 PB2 DIO4 GND DIO0 PB3 DGND GND AOGND PB4 EXTREF GND DAC...

Page 52: ...IGND Input Analog Input Sense AT MIO 64E 3 only This pin serves as the reference node for any of channels ACH 16 63 in NRSE configuration DAC0OUT AOGND Output Analog Channel 0 Output This pin supplies the voltage output of analog output channel 0 This pin is not available on the AT AI 16XE 10 DAC1OUT AOGND Output Analog Channel 1 Output This pin supplies the voltage output of analog output channel...

Page 53: ...FIs or the source for the hardware analog trigger PFI signals are explained in the Timing Connections section later in this chapter The hardware analog trigger is explained in the Analog Trigger section of Chapter 3 Hardware Overview Analog trigger is available only on the AT MIO 16E 1 AT MIO 16E 2 AT MIO 16XE 10 AT AI 16XE 10 and the AT MIO 64E 3 As an output this is the TRIG1 signal In posttrigg...

Page 54: ... WFTRIG DGND Input Output PFI6 Waveform Trigger As an input this is one of the PFIs As an output this is the WFTRIG signal In timed analog output sequences a low to high transition indicates the initiation of the waveform generation PFI7 STARTSCAN DGND Input Output PFI7 Start of Scan As an input this is one of the PFIs As an output this is the STARTSCAN signal This pin pulses once at the start of ...

Page 55: ...00 GΩ in parallel with 100 pF 25 15 200 pA AISENSE AISENSE2 AI 100 GΩ in parallel with 100 pF 25 15 200 pA AIGND AO DAC0OUT AO 0 1 Ω Short circuit to ground 5 at 10 5 at 10 20 V µs DAC1OUT AO 0 1 Ω Short circuit to ground 5 at 10 5 at 10 20 V µs EXTREF AI 10 kΩ 25 15 AOGND AO DGND DO VCC DO 0 1 Ω Short circuit to ground 1 A DIO 0 7 DIO Vcc 0 5 13 at Vcc 0 4 24 at 0 4 1 1 50 kΩ pu1 SCANCLK DO 3 5 a...

Page 56: ...0 kΩ pu PFI8 GPCTR0_SOURCE DIO Vcc 0 5 3 5 at Vcc 0 4 5 at 0 4 1 5 50 kΩ pu PFI9 GPCTR0_GATE DIO Vcc 0 5 3 5 at Vcc 0 4 5 at 0 4 1 5 50 kΩ pu GPCTR0_OUT DO 3 5 at Vcc 0 4 5 at 0 4 1 5 50 kΩ pu FREQ_OUT DO 3 5 at Vcc 0 4 5 at 0 4 1 5 50 kΩ pu 1 DIO 6 7 are also pulled down with a 50 kΩ resistor AI Analog Input DIO Digital Input Output pu pull up AO Analog Output DO Digital Output ADIO Analog Digita...

Page 57: ...d 5 at 10 5 at 10 15 V µs EXTREF AI 10 kΩ 35 25 AOGND AO DGND DO VCC DO 0 1 Ω Short circuit to ground 1A DIO 0 7 DIO Vcc 0 5 13 at Vcc 0 4 24 at 0 4 1 1 50 kΩ pu1 PA 0 7 DIO Vcc 0 5 2 5 at 3 9 2 5 at 0 4 5 100 kΩ pu PB 0 7 DIO Vcc 0 5 2 5 at 3 9 2 5 at 0 4 5 100 kΩ pu PC 0 7 DIO Vcc 0 5 2 5 at 3 9 2 5 at 0 4 5 100 kΩ pu SCANCLK DO 3 5 at Vcc 0 4 5 at 0 4 1 5 50 kΩ pu EXTSTROBE DO 3 5 at Vcc 0 4 5 ...

Page 58: ... 5 at 0 4 1 5 50 kΩ pu PFI9 GPCTR0_GATE DIO Vcc 0 5 3 5 at Vcc 0 4 5 at 0 4 1 5 50 kΩ pu GPCTR0_OUT DO 3 5 at Vcc 0 4 5 at 0 4 1 5 50 kΩ pu FREQ_OUT DO 3 5 at Vcc 0 4 5 at 0 4 1 5 50 kΩ pu 1 DIO 6 7 are also pulled down with a 50 kΩ resistor AI Analog Input DIO Digital Input Output pu pull up AO Analog Output DO Digital Output The tolerance on the 50 kΩ pull up and pull down resistors is very larg...

Page 59: ... 5 at 10 5 at 10 5 V µs AOGND AO DGND DO VCC DO 0 1 Ω Short circuit to ground 1A DIO 0 7 DIO Vcc 0 5 13 at Vcc 0 4 24 at 0 4 1 1 50 kΩ pu SCANCLK DO 3 5 at Vcc 0 4 5 at 0 4 1 5 50 kΩ pu EXTSTROBE DO 3 5 at Vcc 0 4 5 at 0 4 1 5 50 kΩ pu PFI0 TRIG1 DIO Vcc 0 5 3 5 at Vcc 0 4 5 at 0 4 1 5 4 75 kΩ pu PFI1 TRIG2 DIO Vcc 0 5 3 5 at Vcc 0 4 5 at 0 4 1 5 50 kΩ pu PFI2 CONVERT DIO Vcc 0 5 3 5 at Vcc 0 4 5 ...

Page 60: ...put The tolerance on the 50 kΩ pull up and pull down resistors is very large Actual value may range between 17 kΩ and 100 kΩ Table 4 6 I O Signal Summary for the AT MIO 16XE 50 Signal Name Drive Impedance Input Output Protection Volts On Off Source mA at V Sink mA at V Rise Time ns Bias ACH 0 15 AI 20 GΩ in parallelwith 100 pF 25 15 3 nA AISENSE AI 20 GΩ in parallelwith 100 pF 25 15 3 nA AIGND AO ...

Page 61: ...0 4 5 at 0 4 1 5 50 kΩ pu PFI4 GPCTR1_GATE DIO Vcc 0 5 3 5 at Vcc 0 4 5 at 0 4 1 5 50 kΩ pu GPCTR1_OUT DO 3 5 at Vcc 0 4 5 at 0 4 1 5 50 kΩ pu PFI5 UPDATE DIO Vcc 0 5 3 5 at Vcc 0 4 5 at 0 4 1 5 50 kΩ pu PFI6 WFTRIG DIO Vcc 0 5 3 5 at Vcc 0 4 5 at 0 4 1 5 50 kΩ pu PFI7 STARTSCAN DIO Vcc 0 5 3 5 at Vcc 0 4 5 at 0 4 1 5 50 kΩ pu PFI8 GPCTR0_SOURCE DIO Vcc 0 5 3 5 at Vcc 0 4 5 at 0 4 1 5 50 kΩ pu PFI...

Page 62: ...of the AT MIO 64E 3 PGIA In differential mode signals connected to ACH 0 7 16 23 32 39 48 55 are routed to the positive input of the PGIA and signals connected to ACH 8 15 24 31 40 47 56 63 are routed to the negative input of the PGIA Caution Exceeding the differential and common mode input ranges distorts the input signals Exceeding the maximum input voltage rating can damage the AT E Series devi...

Page 63: ...ource With the different configurations you can use the PGIA in different ways Figure 4 4 shows a diagram of the AT E Series device PGIA Figure 4 4 AT E Series PGIA The PGIA applies gain and common mode voltage rejection and presents high input impedance to the analog input signals connected to the AT E Series device Signals are routed to the positive and negative inputs of the PGIA through input ...

Page 64: ...es battery powered devices optical isolator outputs and isolation amplifiers An instrument or device that has an isolated output is a floating signal source You must tie the ground reference of a floating signal to the AT E Series device AIGND to establish a local or onboard reference for the signal Otherwise the measured input signal varies as the source floats out of the common mode input range ...

Page 65: ...ries device for one of three input modes NRSE RSE or DIFF The following sections discuss the use of single ended and differential measurements and considerations for measuring both floating and ground referenced signal sources Figure 4 5 summarizes the recommended input configuration for both types of signal sources ...

Page 66: ...losses Vg are added to measured signal NOT RECOMMENDED V1 ACH ACH AIGND V1 ACH ACH AIGND R See text for information on bias resistors Signal Source Type Floating Signal Source Not Connected to Building Ground Grounded Signal Source Examples Ungrounded Thermocouples Signal Conditioning with Isolated Outputs Battery Devices Examples Plug in Instruments with Nonisolated Outputs Input Differential DIF...

Page 67: ...configuration for every channel up to eight AI channels are available up to 32 channels on the AT MIO 64E 3 In DIFF input mode the AI channels are paired with ACH i as the signal input and ACH i 8 as the signal reference For example ACH0 is paired with ACH8 ACH1 is paired with ACH9 and so on You should use differential input connections for any channel that meets any of the following conditions Th...

Page 68: ...tial Input Connections for Ground Referenced Signals With this type of connection the PGIA rejects both the common mode noise in the signal and the ground potential difference between the signal source and the AT E Series device ground shown as Vcm in Figure 4 6 Selected Channel in DIFF Configuration PGIA Programmable Gain Instrumentation Amplifier Input Multiplexers AISENSE AIGND I O Connector Vc...

Page 69: ...you do not use the resistors and the source is truly floating the source is not likely to remain within the common mode signal range of the PGIA and the PGIA saturates causing erroneous readings You must reference the source to AIGND The easiest way is simply to connect the positive side of the signal to the positive input of the PGIA and connect the negative side of the signal to AIGND as well PG...

Page 70: ...h input impedance of the PGIA You can fully balance the signal path by connecting another resistor of the same value between the positive input and AIGND as shown in Figure 4 7 This fully balanced configuration offers slightly better noise rejection but has the disadvantage of loading the source down with the series combination sum of the two resistors If for example the source impedance is 2 kΩ a...

Page 71: ...input connections are recommended for greater signal integrity for any input signal that does not meet the preceding conditions You can software configure the AT E Series device channels for two different types of single ended connections RSE configuration and NRSE configuration The RSE configuration is used for floating signal sources in this case the AT E Series device provides the reference gro...

Page 72: ...ositive input of the AT E Series PGIA and the signal local ground reference is connected to the negative input of the PGIA The ground point of the signal should therefore be connected to the AISENSE pin Any potential difference between the AT E Series ground and the signal ground appears as a common mode signal at both the positive and negative inputs of the PGIA and this difference is rejected by...

Page 73: ...ases the PGIA can reject any voltage caused by ground potential differences between the signal source and the device In addition with differential input connections the PGIA can reject common mode noise pickup in the leads connecting the signal sources to the device The PGIA can reject common mode signals as long as Vin and Vin are both within 11 V of AIGND The AT MIO 16XE 50 has the additional re...

Page 74: ...s the voltage output signal for AO channel 1 EXTREF is the external reference input for both AO channels You must configure each AO channel individually for external reference selection in order for the signal applied at the external reference input to be used by that channel If you do not specify an external reference the channel uses the internal reference Note You cannot use an external AO refe...

Page 75: ...he DIO port You can program all lines individually to be inputs or outputs The AT MIO 16DE 10 has 24 additional DIO lines configured as three 8 bit ports PA 0 7 PB 0 7 and PC 0 7 You can configure each port for both input and output in various combinations with some handshaking capabilities Caution Exceeding the maximum input voltage ratings which are listed in Tables 4 3 through 4 6 can damage th...

Page 76: ... the switch shown in the figure Digital output applications include sending TTL signals and driving external devices such as the LED shown in the figure Power Connections Two pins on the I O connector supply 5 V from the PC power supply using a self resetting fuse The fuse resets automatically within a few seconds after the overcurrent condition is removed These pins are referenced to DGND and can...

Page 77: ...rogrammable Function Input Connections These PFIs are bidirectional as outputs they are not programmable and reflect the state of many data acquisition waveform generation and general purpose timing signals There are five other dedicated outputs for the remainder of the timing signals As inputs the PFI signals are programmable and can control any data acquisition waveform generation and general pu...

Page 78: ...tor for different applications requiring alternative wiring You can individually enable each of the PFI pins to output a specific internal timing signal For example if you need the CONVERT signal as an output on the I O connector software can turn on the output driver for the PFI2 CONVERT pin You must be careful not to drive a PFI signal externally when it is configured as an output As an input yo...

Page 79: ...be limits imposed by the particular timing signal being controlled These requirements are listed later in this chapter DAQ Timing Connections The DAQ timing signals are TRIG1 TRIG2 STARTSCAN CONVERT AIGATE SISOURCE SCANCLK and EXTSTROBE Posttriggered DAQ allows you to view only data that is acquired after a trigger event is received A typical posttriggered DAQ sequence is shown in Figure 4 13 Pret...

Page 80: ...n for either rising or falling edge The selected edge of the TRIG1 signal starts the DAQ sequence for both posttriggered and pretriggered acquisitions The AT MIO 16E 1 AT MIO 16E 2 AT MIO 16XE 10 AT AI 16XE 10 and AT MIO 64E 3 support analog triggering on the PFI0 TRIG1 pin Refer to Chapter 3 Hardware Overview for more information on analog triggering As an output the TRIG1 signal reflects the act...

Page 81: ...DAQ operation TRIG2 Signal Any PFI pin can externally input the TRIG2 signal which is available as an output on the PFI1 TRIG2 pin Refer to Figure 4 13 for the relationship of TRIG2 to the DAQ sequence As an input the TRIG2 signal is configured in the edge detection mode You can select any PFI pin as the source for TRIG2 and configure the polarity selection for either rising or falling edge The se...

Page 82: ...tion stops This mode acquires data both before and after receiving TRIG2 As an output the TRIG2 signal reflects the posttrigger in a pretriggered acquisition sequence even if the acquisition is being externally triggered by another PFI The TRIG2 signal is not used in posttriggered data acquisition The output is an active high pulse with a pulse width of 50 to 100 ns This output is set to high impe...

Page 83: ...elect internally triggered CONVERT As an output the STARTSCAN signal reflects the actual start pulse that initiates a scan even if the starts are being externally triggered by another PFI You have two output options The first is an active high pulse with a pulse width of 50 to 100 ns which indicates the start of the scan The second action is an active high pulse that terminates at the start of the...

Page 84: ...pulses should be separated by at least one scan period A counter on the AT E Series device internally generates the STARTSCAN signal unless you select some external source This counter is started by the TRIG1 signal and is stopped either by software or by the sample counter Scans generated by either an internal or external STARTSCAN signal are inhibited unless they occur within a DAQ sequence Scan...

Page 85: ...or either rising or falling edge The selected edge of the CONVERT signal initiates an A D conversion As an output the CONVERT signal reflects the actual convert pulse that is connected to the ADC even if the conversions are being externally generated by another PFI The output is an active low pulse with a pulse width of 50 to 100 ns This output is set to high impedance at startup Figures 4 21 and ...

Page 86: ...k off scans in a DAQ sequence You can configure the PFI pin you select as the source for the AIGATE signal in the level detection mode You can configure the polarity selection for the PFI pin for either active high or active low In the level detection mode if AIGATE is active the STARTSCAN signal is masked off and no scans can occur The AIGATE signal can neither stop a scan in progress nor continu...

Page 87: ...to 100 ns after an A D conversion begins The polarity of this output is software selectable but is typically configured so that a low to high leading edge can clock external AI multiplexers indicating when the input signal has been sampled and can be removed This signal has a 400 to 500 ns pulse width and is software enabled Figure 4 24 shows the timing for the SCANCLK signal Note When using NI DA...

Page 88: ...tions The analog group defined for the AT E Series device is controlled by WFTRIG UPDATE and UISOURCE WFTRIG Signal Any PFI pin can externally input the WFTRIG signal which is available as an output on the PFI6 WFTRIG pin As an input the WFTRIG signal is configured in the edge detection mode You can select any PFI pin as the source for WFTRIG and configure the polarity selection for either rising ...

Page 89: ...de You can select any PFI pin as the source for UPDATE and configure the polarity selection for either rising or falling edge The selected edge of the UPDATE signal updates the outputs of the DACs In order to use UPDATE you must set the DACs to posted update mode As an output the UPDATE signal reflects the actual update pulse that is connected to the DACs even if the updates are being externally g...

Page 90: ...re 4 28 UPDATE Input Signal Timing Figure 4 29 UPDATE Output Signal Timing The DACs are updated within 100 ns of the leading edge Separate the UPDATE pulses with enough time that new data can be written to the DAC latches The AT E Series device UI counter normally generates the UPDATE signal unless you select some external source The UI counter is started by the WFTRIG signal and can be stopped by...

Page 91: ...ncy is 20 MHz with a minimum pulse width of 23 ns high or low There is no minimum frequency limitation Either the 20 MHz or 100 kHz internal timebase normally generates the UISOURCE signal unless you select some external source General Purpose Timing Signal Connections The general purpose timing signals are GPCTR0_SOURCE GPCTR0_GATE GPCTR0_OUT GPCTR0_UP_DOWN GPCTR1_SOURCE GPCTR1_GATE GPCTR1_OUT GP...

Page 92: ...ess you select some external source GPCTR0_GATE Signal Any PFI pin can externally input the GPCTR0_GATE signal which is available as an output on the PFI9 GPCTR0_GATE pin As an input the GPCTR0_GATE signal is configured in the edge detection mode You can select any PFI pin as the source for GPCTR0_GATE and configure the polarity selection for either rising or falling edge You can use the gate sign...

Page 93: ...oftware selectable for both options This output is set to high impedance at startup Figure 4 33 shows the timing of the GPCTR0_OUT signal Figure 4 33 GPCTR0_OUT Signal Timing GPCTR0_UP_DOWN Signal This signal can be externally input on the DIO6 pin and is not available as an output on the I O connector The general purpose counter 0 counts down when this pin is at a logic low and counts up when it ...

Page 94: ... requirements for the GPCTR1_SOURCE signal Figure 4 34 GPCTR1_SOURCE Signal Timing The maximum allowed frequency is 20 MHz with a minimum pulse width of 10 ns high or low There is no minimum frequency limitation The 20 MHz or 100 kHz timebase normally generates the GPCTR1_SOURCE unless you select some external source GPCTR1_GATE Signal Any PFI pin can externally input the GPCTR1_GATE signal which ...

Page 95: ...nter 1 You have two software selectable output options pulse on TC and toggle output polarity on TC The output polarity is software selectable for both options This output is set to high impedance at startup Figure 4 36 shows the timing requirements for the GPCTR1_OUT signal Figure 4 36 GPCTR1_OUT Signal Timing GPCTR1_UP_DOWN Signal This signal can be externally input on the DIO7 pin and is not av...

Page 96: ...the counter is programmed to count falling edges The GATE input timing parameters are referenced to the signal at the SOURCE input or to one of the internally generated signals on the AT E Series device Figure 4 37 shows the GATE signal referenced to the rising edge of a source signal The gate must be valid either high or low for at least 10 ns before the rising or falling edge of a source signal ...

Page 97: ...ounter that can divide its input clock by the numbers 1 through 16 The input clock of the frequency generator is software selectable from the internal 10 MHz and 100 kHz timebases The output polarity is software selectable This output is set to high impedance at startup Timing Specifications for Digital I O Ports A B and C AT MIO 16DE 10 only In addition to its function as a digital I O port digit...

Page 98: ...ledge Input A low signal on this handshaking line indicates that the data written from the selected port has been accepted This signal is a response from the external device that it has received the data from the AT MIO 16DE 10 OBF Output Output Buffer Full A low signal on this handshaking line indicates that data has been written from the selected port INTR Output Interrupt Request This signal be...

Page 99: ...for an input transfer in Mode 1 Figure 4 38 Mode 1 Input Timing Name Description Minimum Maximum T1 STB Pulse Width 100 T2 STB 0 to IBF 1 150 T3 Data before STB 1 20 T4 STB 1 to INTR 1 150 T5 Data after STB 1 50 T6 RD 0 to INTR 0 200 T7 RD 1 to IBF 0 150 All timing values are in nanoseconds DATA RD INTR IBF STB T1 T2 T4 T7 T6 T3 T5 ...

Page 100: ...the timing specifications for an output transfer in Mode 1 Figure 4 39 Mode 1 Output Timing Name Description Minimum Maximum T1 WR 0 to INTR 0 250 T2 WR 1 to Output 200 T3 WR 1 to OBF 0 150 T4 ACK 0 to OBF 1 150 T5 ACK Pulse Width 100 T6 ACK 1 to INTR 1 150 All timing values are in nanoseconds WR OBF INTR ACK DATA T1 T2 T3 T4 T5 T6 ...

Page 101: ...de 2 Bidirectional Timing Name Description Minimum Maximum T1 WR 1 to OBF 0 150 T2 Data before STB 1 20 T3 STB Pulse Width 100 T4 STB 0 to IBF 1 150 T5 Data after STB 1 50 T6 ACK 0 to OBF 1 150 T7 ACK Pulse Width 100 T8 ACK 0 to Output 150 T9 ACK 1 to Output Float 20 250 T10 RD 1 to IBF 0 150 All timing values are in nanoseconds T1 T6 T7 T3 T4 T10 T2 T5 T8 T9 WR OBF INTR ACK STB IBF RD DATA ...

Page 102: ...gnals traveling through areas with large magnetic fields or high electromagnetic interference Route signals to the device carefully Keep cabling away from noise sources The most common noise source in a PC DAQ system is the video monitor Separate the monitor from the analog signals as much as possible The following recommendations apply for all signal connections to the AT E Series device Separate...

Page 103: ...curate Loading Calibration Constants The AT E Series device is factory calibrated before shipment at approximately 25 C to the levels indicated in Appendix A Specifications The associated calibration constants the values that were written to the CalDACs to achieve calibration in the factory are stored in the onboard nonvolatile memory EEPROM Because the CalDACs have no memory capability they do no...

Page 104: ...ount of gain error and self calibration should be sufficient External Calibration The AT E Series device has an onboard calibration reference to ensure the accuracy of self calibration Its specifications are listed in Appendix A Specifications The reference voltage is measured at the factory and stored in the EEPROM for subsequent self calibrations This voltage is stable enough for most applicatio...

Page 105: ...alibration Other Considerations The CalDACs adjust the gain error of each AO channel by adjusting the value of the reference voltage supplied to that channel This calibration mechanism is designed to work only with the internal 10 V reference Thus in general it is not possible to calibrate the AO gain error when using an external reference In this case it is advisable to account for the nominal ga...

Page 106: ...64E 3 Analog Input Input Characteristics Number of channels AT MIO 16E 1 AT MIO 16E 2 16 single ended or 8 differential software selectable AT MIO 64E 3 64 single ended or 32 differential software selectable Type of ADC Successive approximation Resolution 12 bits 1 in 4 096 Max sampling rate AT MIO 16E 1 1 25 MS s guaranteed AT MIO 16E 2 AT MIO 64E 3 500 kS s guaranteed Throughput to system memory...

Page 107: ...cted 100 pin devices ACH 0 63 AISENSE AISENSE2 68 pin devices ACH 0 15 AISENSE FIFO buffer size AT MIO 16E 1 8 192 samples AT MIO 16E 2 AT MIO 64E 3 2 048 samples Data transfers DMA interrupts programmed I O DMA modes Single transfer demand transfer Configuration memory size 512 words Range Software Selectable Input Range Bipolar Unipolar 20 V 10 V 10 V 5 V 0 to 10 V 5 V 2 5 V 0 to 5 V 2 V 1 V 0 t...

Page 108: ...alibration 2 5 mV max Postgain error after calibration 0 5 mV max Postgain error before calibration 100 mV max Gain error relative to calibration reference After calibration gain 1 0 02 of reading max Before calibration 2 5 of reading max Gain 1 with gain error adjusted to 0 at gain 1 0 02 of reading max Amplifier Characteristics Input impedance Normal powered on 100 GΩ in parallel with 100 pF Pow...

Page 109: ... typ 3 µs max 1 5 µs typ 2 µs max 1 5 µs typ 2 µs max 1 2 µs typ 3 µs max 1 5 µs typ 2 µs max 1 3 µs typ 1 5 µs max 2 to 50 2 µs typ 3 µs max 1 5 µs typ 2 µs max 0 9 µs typ 1 µs max 100 2 µs typ 3 µs max 1 5 µs typ 2 µs max 1 µs typ 1 5 µs max AT MIO 16E 2 All 2 µs typ 4 µs max 1 9 µs typ 2 µs max 1 8 µs typ 2 µs max AT MIO 64E 3 All 3 µs typ 5 µs max 2 µs typ 3 µs max 1 8 µs typ 2 µs max Accuracy...

Page 110: ...rature coefficient Pregain 5 µV C Postgain 240 µV C Gain temperature coefficient 20 ppm C Analog Output Output Characteristics Number of channels 2 voltage Resolution 12 bits 1 in 4 096 Max update rate FIFO mode waveform generation Internally timed 1 MS s per channel Externally timed 950 kS s per channel Gain Noise Dither Off Noise Dither On AT MIO 16E 1 0 5 to 10 0 25 0 5 20 0 4 0 6 50 0 5 0 7 10...

Page 111: ...ingle transfer demand transfer Transfer Characteristics Relative accuracy INL After calibration 0 3 LSB typ 0 5 LSB max Before calibration 4 LSB max DNL After calibration 0 3 LSB typ 1 0 LSB max Before calibration 3 LSB max Monotonicity 12 bits guaranteed after calibration Offset error After calibration 1 0 mV max Before calibration 200 mV max Gain error relative to internal reference After calibr...

Page 112: ...te 0 V 200 mV External reference input Range 11 V Overvoltage protection 25 V powered on 15 V powered off Input impedance 10 kΩ Bandwidth 3 dB 1 MHz Dynamic Characteristics Settling time for full scale step 3 µs to 0 5 LSB accuracy Slew rate 20 V µs Noise 200 µVrms DC to 1 MHz Glitch energy at midscale transition Magnitude Reglitching disabled 200 mV Reglitching enabled 30 mV Duration 1 5 µs Stabi...

Page 113: ...able rate 1 to 10 kwords s typical Timing I O Number of channels 2 up down counter timers 1 frequency scaler Resolution Counter timers 24 bits Frequency scalers 4 bits Compatibility TTL CMOS Base clocks available Counter timers 20 MHz 100 kHz Frequency scalers 10 MHz 100 kHz Base clock accuracy 0 01 Max source frequency 20 MHz Level Min Max Input low voltage 0 V 0 8 V Input high voltage 2 V 5 V In...

Page 114: ...er Triggers Analog Trigger Source ACH 0 63 PFI0 TRIG1 Level full scale internal 10 V external Slope Positive or negative software selectable Resolution 8 bits 1 in 256 Hysteresis Programmable Bandwidth 3 dB 1 5 MHz internal 7 MHz external External input PFI0 TRIG1 Impedance 10 kΩ Coupling DC Protection 0 5 to Vcc 0 5 V when configured as a digital signal 35 V when configured as an analog trigger s...

Page 115: ...n reference Level 5 000 V 3 5 mV over full operating temperature actual value stored in EEPROM Temperature coefficient 5 ppm C max Long term stability 15 ppm Bus Interface Type Slave Power Requirement 5 VDC 5 1 0 A Power available at I O connector 4 65 VDC to 5 25 VDC at 1 A Physical Dimensions not including connectors 33 8 by 9 9 cm 13 3 by 3 9 in I O connector AT MIO 16E 1 AT MIO 16E 2 68 pin ma...

Page 116: ...y and electrical equipment for measurement control and laboratory use EN 61010 1 1993 A2 1995 IEC 61010 1 1990 A2 1995 UL 3101 1 1993 UL 3111 1 1994 UL 3121 1998 CAN CSA c22 2 no 1010 1 1992 A2 1997 Electromagnetic Compatibility CE C Tick and FCC Part 15 Class A Compliant Electrical emissions EN 55011 Class A at 10 m FCC Part 15A above 1 GHz Electrical immunity Evaluated to EN 61326 1998 Table 1 N...

Page 117: ...gle ended or 8 differential software selectable Type of ADC Successive approximation Resolution 12 bits 1 in 4 096 Max sampling rate 100 kS s guaranteed Input signal ranges Input coupling DC Max working voltage signal common mode Each input should remain within 11 V of ground Overvoltage protection 35 V powered on 25 V powered off Range Software Selectable Input Range Bipolar Unipolar 20 V 10 V 10...

Page 118: ... LSB max undithered DNL 0 2 LSB typ 1 0 LSB max No missing codes 12 bits guaranteed Offset error Pregain error after calibration 2 µV max Pregain error before calibration 24 mV max Postgain error after calibration 0 5 mV max Postgain error before calibration 100 mV max Gain error relative to calibration reference After calibration Gain 1 0 01 of reading max Before calibration 2 0 of reading max Ga...

Page 119: ...µs max to 0 5 LSB accuracy System noise not including quantization Crosstalk DC to 100 kHz Adjacent channels 60 dB All other channels 80 dB Stability Offset temperature coefficient Pregain 15 µV C Postgain 240 µV C Gain temperature coefficient 20 ppm C Analog Output Output Characteristics Number of channels 2 voltage Resolution 12 bits 1 in 4 096 1 Source impedance 1 kΩ Gain Noise Dither Off Noise...

Page 120: ...NL After calibration 0 3 LSB typ 0 5 LSB max Before calibration 4 LSB max DNL After calibration 0 3 LSB typ 1 0 LSB max Before calibration 3 LSB max Monotonicity 12 bits guaranteed after calibration Offset error After calibration 1 0 mV max Before calibration 200 mV max Gain error relative to internal reference After calibration 0 01 of output max Before calibration 0 5 of output max Gain error re...

Page 121: ...ed off Input impedance 10 kΩ Bandwidth 3 dB 300 kHz Dynamic Characteristics Settling time for full scale step 10 µs to 0 5 LSB accuracy Slew rate 10 V µs Noise 200 µVrms DC to 1 MHz Glitch energy at midscale transition Magnitude 100 mV Duration 3 µs Stability Offset temperature coefficient 50 µV C Gain temperature coefficient Internal reference 25 ppm C External reference 25 ppm C Digital I O Numb...

Page 122: ...terrupts programmed I O Max transfer rate 1 word 8 bits 50 kwords s system dependent Constant sustainable rate 1 to 10 kwords s typical Level Min Max Input low voltage 0 V 0 8 V Input high voltage 2 V 5 V Input low current Vin 0 V 320 µA Input high current Vin 5 V 10 µA Output low voltage IOL 24 mA 0 4 V Output high voltage IOH 13 mA 4 35 V Level Min Max Input low voltage 0 V 0 8 V Input high volt...

Page 123: ...L CMOS Base clocks available Counter timers 20 MHz 100 kHz Frequency scaler 10 MHz 100 kHz Base clock accuracy 0 01 Max source frequency 20 MHz Min source pulse duration 10 ns in edge detect mode Min gate pulse duration 10 ns in edge detect mode Data transfers DMA interrupts programmed I O DMA modes Single transfer demand transfer Triggers Digital Trigger Compatibility TTL Response Rising or falli...

Page 124: ...ature coefficient 5 ppm C max Long term stability 15 ppm Bus Interface Type Slave Power Requirement 5 VDC 5 0 7 A Power available at I O connector 4 65 VDC to 5 25 VDC at 1 A Physical Dimensions not including connectors 17 45 by 10 56 cm 6 87 by 4 16 in I O connector AT MIO 16E 10 68 pin male SCSI II type AT MIO 16DE 10 100 pin female 0 050 D type Maximum Working Voltage Maximum working voltage re...

Page 125: ...7 Electromagnetic Compatibility CE C Tick and FCC Part 15 Class A Compliant Electrical emissions EN 55011 Class A at 10 m FCC Part 15A above 1 GHz Electrical immunity Evaluated to EN 61326 1998 Table 1 Note For full EMC compliance you must operate this device with shielded cabling In addition all covers and filler panels must be installed Refer to the Declaration of Conformity DoC for this product...

Page 126: ...mation Resolution 16 bits 1 in 65 536 Maximum sampling rate 100 kS s guaranteed Input signal ranges Input coupling DC Maximum working voltage Each input should remain within 11 V of ground Overvoltage protection 25 V powered on 15 V powered off Inputs protected ACH 0 15 AISENSE Range Software Selectable Input Range Bipolar Unipolar 20 V 10 V 10 V 5 V 0 to 10 V 5 V 0 to 5 V 4 V 2 V 2 V 1 V 0 to 2 V...

Page 127: ...teed Offset error Pregain error after calibration 3 µV max Pregain error before calibration 2 2 mV max Postgain error after calibration 76 µV max Postgain error before calibration 102 mV max Gain error relative to calibration reference After calibration gain 1 30 5 ppm of reading max Before calibration 2 150 ppm of reading max With gain error adjusted to 0 at gain 1 Gain 1 200 ppm of reading Ampli...

Page 128: ...MRR Bipolar CMRR Unipolar 20 V 92 dB 10 V 97 dB 92 dB 5 V 97 dB 4 V 101 dB 2 V 104 dB 101 dB 1 V 105 dB 104 dB 100 mV to 500 mV 105 dB 105 dB Accuracy 0 00076 0 5 LSB 0 0015 1 LSB 0 0016 4 LSB 40 µs max 20 µs max 10 µs max Accuracy values valid for source impedances 1 kΩ Refer to the Multiple Channel Scanning Considerations section of Chapter 3 Hardware Overview for more information Range Bipolar ...

Page 129: ...t 7 ppm C Analog Output AT MIO 16XE 10 only Output Characteristics Number of channels 2 voltage Resolution 16 bits 1 in 65 536 Max update rate 100 kS s Type of DAC Double buffered FIFO buffer size 2 048 samples Data transfers DMA interrupts programmed I O DMA modes Single transfer demand transfer Transfer Characteristics Relative accuracy INL 0 5 LSB typ 1 LSB max DNL 1 LSB max Monotonicity 16 bit...

Page 130: ...tput coupling DC Output impedance 0 1 Ω Current drive 5 mA Protection Short circuit to ground Power on state 0 V 20 mV Dynamic Characteristics Settling time for full scale step 10 µs to 1 LSB accuracy Slew rate 5 V µs Noise 60 µVrms DC to 1 MHz Stability Offset temperature coefficient 50 µV C Gain temperature coefficient 7 5 ppm C Digital I O Number of channels 8 input output Compatibility TTL CMO...

Page 131: ... scaler Resolution Counter timers 24 bits Frequency scaler 4 bits Compatibility TTL CMOS Base clocks available Counter timers 20 MHz 100 kHz Frequency scaler 10 MHz 100 kHz Base clock accuracy 0 01 Max source frequency 20 MHz Min source pulse duration 10 ns edge detect mode Min gate pulse duration 10 ns edge detect mode Data transfers DMA interrupts programmed I O DMA modes Single transfer demand ...

Page 132: ...re selectable Resolution 12 bits 1 in 4 096 Hysteresis Programmable Bandwidth 3 dB 255 kHz internal 4 MHz external External input PFI0 TRIG1 Impedance 10 kΩ Coupling DC Protection 0 5 to Vcc 0 5 V when configured as a digital signal 35 V when configured as an analog trigger signal or disabled 35 V powered off Accuracy 1 of full scale range Digital Trigger Compatibility TTL Response Rising or falli...

Page 133: ...d in EEPROM Temperature coefficient 0 6 ppm C max Long term stability 6 ppm Bus Interface Type Slave Power Requirement 5 VDC 5 1 2 A Power available at I O connector 4 65 VDC to 5 25 VDC at 1 A Physical Dimensions not including connectors 33 8 by 9 9 cm 13 3 by 3 9 in I O connector 68 pin male SCSI II type Maximum Working Voltage Maximum working voltage refers to the signal voltage plus the common...

Page 134: ...1 1992 A2 1997 Electromagnetic Compatibility CE C Tick and FCC Part 15 Class A Compliant Electrical emissions EN 55011 Class A at 10 m FCC Part 15A above 1 GHz Electrical immunity Evaluated to EN 61326 1998 Table 1 Note For full EMC compliance you must operate this device with shielded cabling In addition all covers and filler panels must be installed Refer to the Declaration of Conformity DoC for...

Page 135: ... Maximum sampling rate 20 kS s guaranteed Input signal ranges Input coupling DC Maximum working voltage signal common mode The average voltage of each differential pair should remain within 8 V of ground Overvoltage protection 25 V powered on 15 V powered off Inputs protected ACH 0 15 AISENSE FIFO buffer size 512 samples Range Software Selectable Input Range Bipolar Unipolar 20 V 10 V 10 V 5 V 0 t...

Page 136: ... error after calibration 3 µV max Pregain error before calibration 1 mV max Postgain error after calibration 76 µV max Postgain error before calibration 4 mV max Gain error relative to calibration reference After calibration gain 1 30 5 ppm of reading max Before calibration 2 250 ppm of reading max With gain error adjusted to 0 at gain 1 Gain 2 10 100 ppm of reading Gain 100 250 ppm of reading Amp...

Page 137: ... dB 2 V 100 dB 1 V 100 dB 200 mV 120 dB 100 mV 120 dB Range Small Signal 3dB 5 to 20 V 63 kHz 1 to 2 V 57 kHz 100 to 200 mV 33 kHz Range Accuracy 0 0015 1 LSB 0 0061 4 LSB 1 to 20 V 50 µs max 50 µs max 200 mV bipolar 75 µs max 50 µs max 100 mV unipolar 75 µs max 50 µs max Accuracy values valid for source impedances 1 kΩ Refer to the Multiple Channel Scanning Considerations section of Chapter 3 Har...

Page 138: ...Postgain 12 µV C Gain temperature coefficient 5 ppm C Analog Output Output Characteristics Number of channels 2 voltage Resolution 12 bits 1 in 4 096 Max update rate 20 kS s system dependent Type of DAC Double buffered FIFO buffer size None Data transfers DMA interrupts programmed I O DMA modes Single transfer demand transfer Transfer Characteristics Relative accuracy INL 0 5 LSB max DNL 1 LSB max...

Page 139: ...ange 10 V Output coupling DC Output impedance 0 1 Ω max Current drive 5 mA Protection Short circuit to ground Power on state 0 V 85 mV Dynamic Characteristics Settling time for full scale step 50 µs to 0 5 LSB accuracy Slew rate 2 V µs Noise 40 µVrms DC to 1 MHz Glitch energy at midscale transition Magnitude 30 mV Duration 10 µs Stability Offset temperature coefficient 25 µV C Gain temperature coe...

Page 140: ...nter timers 1 frequency scaler Resolution Counter timers 24 bits Frequency scaler 4 bits Compatibility TTL CMOS Base clocks available Counter timers 20 MHz 100 kHz Frequency scaler 10 MHz 100 kHz Base clock accuracy 0 01 Max source frequency 20 MHz Min source pulse duration 10 ns edge detect mode Min gate pulse duration 10 ns edge detect mode Level Min Max Input low voltage 0 V 0 8 V Input high vo...

Page 141: ...ns min RTSI Trigger Lines 7 Calibration Recommended warm up time 15 min Calibration interval 1 year External calibration reference 6 and 9 999V Onboard calibration reference Level 5 000 V 3 mV over full operating temperature actual value stored in EEPROM Temperature coefficient 2 ppm C max Long term stability 15 ppm Bus Interface Type Slave Power Requirement 5 VDC 5 0 75 A Power available at I O c...

Page 142: ...arth 42 V Installation Category II Channel to channel 42 V Installation Category II Environmental Operating temperature 0 to 55 C Storage temperature 20 to 70 C Humidity 10 to 90 RH noncondensing Maximum altitude 2 000 meters Pollution degree indoor use only 2 Safety The DAQ device meets the requirements of the following standards for safety and electrical equipment for measurement control and lab...

Page 143: ... appears in Adobe Acrobat format Click the Acrobat icon to download or read the DoC Maximum Signal Ratings for AT Series Devices Note NI is not liable for any damage resulting from signal connections that exceed these ratings Refer to the warranty for specific information on warranty coverage Connections that exceed any of the maximum ratings of input signals on the data acquisition DAQ devices li...

Page 144: ...FI0 5 5 to 0 5 V3 35 V4 5 5 to 0 5 V3 0 5 V5 5 5 to 0 5 V3 0 5 V5 PFI 1 9 5 5 to 0 5 V3 0 5 V5 5 5 to 0 5 V3 0 5 V5 5 5 to 0 5 V3 0 5 V5 DIO x 5 5 to 0 5 V3 0 5 V5 5 5 to 0 5 V3 0 5 V5 5 5 to 0 5 V3 0 5 V5 PA PB PC x N A N A 5 5 to 0 5 V3 6 0 5 V5 6 N A N A DACxOUT Output only EXTSTROBE Output only SCANCLK Output only GPCTR0_OUT Output only FREQ_OUT Output only VCC Output only 1 N A for AT MIO 16X...

Page 145: ...g add signal conditioning circuitry to the signal in question to either attenuate or clip the voltage signal If dynamic for example AC signals are connected to the inputs you must anticipate or calculate the maximum voltage that the signal may attain Again if you suspect it will exceed the maximum signal rating allowed for the selected signal you should add protection or signal conditioning circui...

Page 146: ...devices Figure B 1 shows the pin assignments for the 68 pin MIO connector This connector is available when you use the SH6868 EP or R6868 cable assemblies with the AT MIO 16E 1 AT MIO 16E 2 AT MIO 16E 10 AT MIO 16XE 10 AT AI 16XE 10 or AT MIO 16XE 50 It is also one of the two 68 pin connectors available when you use the SH1006868 cable assembly with the AT MIO 16DE 10 or AT MIO 64E 3 ...

Page 147: ...IO1 DGND DIO4 EXTREF2 DAC1OUT 1 DAC0OUT 1 ACH15 AIGND ACH6 ACH13 AIGND ACH4 AIGND ACH3 ACH10 AIGND ACH1 ACH8 DGND PFI8 GPCTR0_SOURCE PFI7 STARTSCAN GPCTR1_OUT PFI4 GPCTR1_GATE PFI3 GPCTR1_SOURCE PFI2 CONVERT DGND DGND DGND EXTSTROBE SCANCLK DIO3 DIO7 DIO2 DGND DIO5 DIO0 DGND AOGND AOGND AIGND ACH7 ACH14 AIGND ACH5 ACH12 AISENSE ACH11 AIGND ACH2 ACH9 AIGND ACH0 1 35 2 36 3 37 4 38 5 39 6 40 7 41 8 ...

Page 148: ...8 Pin DIO Connector Pin Assignments N C N C N C N C N C N C N C N C N C 5V PA0 GND PA2 PA3 GND PA5 PA6 GND PB0 PB1 GND GND PB4 PB5 GND PB7 PC0 GND PC2 PC3 GND PC5 PC6 GND N C N C N C N C N C N C N C N C N C GND GND PA1 GND GND PA4 GND GND PA7 GND GND PB2 PB3 GND GND PB6 GND GND PC1 GND GND PC4 GND GND PC7 1 35 2 36 3 37 4 38 5 39 6 40 7 41 8 42 9 43 10 44 11 45 12 46 13 47 14 48 15 49 16 50 17 51 ...

Page 149: ... 54 ACH 61 ACH 52 ACH 51 ACH 58 ACH 49 ACH 48 ACH 47 ACH 38 ACH 37 ACH 44 AIGND ACH 35 ACH 34 ACH 41 ACH 32 ACH 23 ACH 30 ACH 21 ACH 20 ACH 27 ACH 18 ACH 17 ACH 24 N C N C N C N C N C N C N C N C N C ACH 63 ACH 62 ACH 53 ACH 60 ACH 59 ACH 50 ACH 57 ACH 56 ACH 39 ACH 46 ACH 45 ACH 36 AISENSE2 ACH 43 ACH 42 ACH 33 ACH 40 ACH 31 ACH 22 ACH 29 ACH 28 ACH 19 ACH 26 ACH 25 ACH 16 1 35 2 36 3 37 4 38 5 3...

Page 150: ... cable assembly with the AT MIO 16DE 10 or AT MIO 64E 3 Figure B 4 50 Pin MIO Connector Pin Assignments GPCTR0_OUT PFI8 GPCTR0_SOURCE PFI6 WFTRIG GPCTR1_OUT PFI3 GPCTR1_SOURCE PFI1 TRIG2 EXTSTROBE 5V DGND DIO3 DIO2 DIO1 DIO0 AOGND DAC1OUT AISENSE ACH7 ACH6 ACH5 ACH4 ACH3 ACH2 ACH1 ACH0 AIGND FREQ_OUT PFI7 STARTSCAN PFI5 UPDATE PFI2 CONVERT PFI0 TRIG1 SCANCLK 5V PFI9 GPCTR0_GATE PFI4 GPCTR1_GATE DI...

Page 151: ...ble assembly with the AT MIO 16DE 10 Figure B 5 50 Pin DIO Connector Pin Assignments 5V PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 49 50 47 48 45 46 43 44 41 42 39 40 37 38 35 36 33 34 31 32 29 30 27 28 25 26 23 24 21 22 19 20 17 18 15 16 13 14 11...

Page 152: ...ure B 6 50 Pin Extended AI Connector Pin Assignments ACH55 ACH54 ACH53 ACH52 ACH51 ACH50 ACH49 ACH48 ACH39 ACH38 ACH37 ACH36 AISENSE2 ACH35 ACH34 ACH33 ACH32 ACH23 ACH22 ACH21 ACH20 ACH19 ACH18 ACH17 ACH16 ACH63 ACH61 ACH60 ACH58 ACH57 ACH56 ACH47 ACH62 ACH59 ACH46 ACH45 ACH44 AIGND ACH43 ACH42 ACH41 ACH40 ACH31 ACH30 ACH29 ACH28 ACH27 ACH26 ACH25 ACH24 49 50 47 48 45 46 43 44 41 42 39 40 37 38 35...

Page 153: ...it counters Analog output three 24 bit one 16 bit counters General purpose counter timer functions two 24 bit counters The groups can be configured independently with timing resolutions of 50 ns or 10 µs With the DAQ STC you can interconnect a wide variety of internal timing signals to other internal blocks The interconnection scheme is quite flexible and completely software configurable New capab...

Page 154: ... NI DAQ version 6 6 or earlier Installing and Configuring the Device How do you set the base address for an AT E Series device Windows NT will automatically detect an AT E Series device However you must use the Measurement Automation Explorer MAX to assign the base address For Windows 95 the base address can be changed in the Device Manager For Windows 2000 XP Me 9x the operating system detects th...

Page 155: ...xcellent tools for performing simple functional tests of the device such as analog input digital I O and counter timer tests I have several DAQ devices that use more total interrupt and DMA channels than I have available in my PC What should I do Visit ni com support daq for operating system specific troubleshooting instructions Analog Input and Output I m using my device in differential AI mode a...

Page 156: ... device Yes One way to accomplish this synchronization is to use the waveform generation timing pulses to control the AI data acquisition To do this follow steps 1 through 4 in addition to the usual steps for data acquisition and waveform generation configuration 1 Enable the PFI5 line for output as follows If you are using NI DAQ call Select_Signal deviceNumber ND_PFI_5 ND_OUT_UPDATE ND_HIGH_TO_L...

Page 157: ...ded configuration To enable multi mode scanning in LabVIEW you would use the coupling input config cluster input of the AI Config VI This input has a 1 to 1 correspondence with the channels array input of the AI Config VI Therefore you must list all channels either individually or in groups of channels with the same input configuration For example if you want Channel 0 to be differential and Chann...

Page 158: ...n and sampling channels at different gains refer to Chapter 3 Hardware Overview How are the AI channels of the AT MIO 64E 3 addressed when they are used in differential mode The 32 differential channel pairs are addressed as shown in the following table How can I use STARTSCAN and CONVERT on my device to sample my AI channel s An E series device employs both the STARTSCAN and CONVERT signals to pe...

Page 159: ...ntrast to the Am9513 The DAQ STC incorporates much more than just 10 Am9513 style counters within one chip In fact the DAQ STC has the complexity of more than 24 chips The DAQ STC makes possible PFI lines analog triggering selectable logic level and frequency shift keying The DAQ STC also makes buffered operations possible such as direct up down control single or pulse train generation equivalent ...

Page 160: ... the GPCTR functions ICTR and CTR functions do not work with the DAQ STC The GPCTR functions have the same capabilities as the ICTR and CTR functions plus more but you must rewrite the application with the GPCTR function calls I m using one of the general purpose counter timers on my AT E Series device but I do not see the counter timer output on the I O connector What am I doing wrong If you are ...

Page 161: ...ls together If you are using NI DAQ with LabVIEW and you want to connect external signal sources to the PFI lines you can use AI Clock Config AI Trigger Config AO Clock Config AO Trigger and Gate Config and Counter Set Attribute advanced level VIs to indicate which function the connected signal serves Use the Route Signal VI to enable the PFI lines to output internal signals Caution If you enable ...

Page 162: ... driving the output either high or low However these lines may have pull up or pull down resistors connected to them as shown in Tables 4 2 to 4 5 These resistors weakly pull the output to either a logic high or logic low state For example DIO 0 is in the high impedance state after power on and Table 4 2 I O Signal Summary for the AT E Series shows that there is a 50 kΩ pull up resistor This pull ...

Page 163: ... Assisted Support Options Contact NI engineers and other measurement and automation professionals by visiting ni com ask Our online system helps you define your question and connects you to the experts by phone discussion forum or email Training Visit ni com custed for self paced tutorials videos and interactive CDs You also can register for instructor led hands on courses at locations around the ...

Page 164: ...fix Meaning Value p pico 10 12 n nano 10 9 µ micro 10 6 m milli 10 3 k kilo 103 M mega 106 G giga 109 Numbers Symbols percent plus or minus degrees per positive of or plus negative of or minus Ω ohms square root of 5V 5 VDC source signal A A amperes A D analog to digital 000 ...

Page 165: ... input sense 2 signal ANSI American National Standards Institute AOGND analog output ground signal ASIC application specific integrated circuit B BIOS basic input output system or built in operating system C C Celsius CalDAC calibration DAC channel rate reciprocal of the interchannel delay CMOS complementary metal oxide semiconductor CMRR common mode rejection ratio CONVERT convert signal D D A di...

Page 166: ...t output DMA direct memory access DNL differential nonlinearity E EEPROM electrically erasable programmable read only memory EISA Extended Industry Standard Architecture EXTREF external reference signal EXTSTROBE external strobe signal F FIFO first in first out FREQ_OUT frequency output signal ft feet G GPCTR0_GATE general purpose counter 0 gate signal GPCTR1_GATE general purpose counter 1 gate si...

Page 167: ...at passes between sampling consecutive channels The interchannel delay must be short enough to allow sampling of all the channels in the channel list within the scan interval The greater the interchannel delay the more time the PGIA is allowed to settle before the next channel is sampled The interchannel delay is regulated by CONVERT I O input output IOH current output high IOL current output low ...

Page 168: ...nonreferenced single ended mode O OUT output P PC personal computer PFI Programmable Function Input PGIA Programmable Gain Instrumentation Amplifier ppm parts per million R reglitch to modify the glitches in a signal in order to make them less disruptive rms root mean square RSE referenced single ended mode RTD resistive temperature device RTSI Real Time System Integration ...

Page 169: ... STARTSCAN scan rate reciprocal of the scan interval SCXI Signal Conditioning eXtensions for Instrumentation SE single ended inputs SISOURCE SI counter clock signal STARTSCAN start scan signal T TC terminal count THD total harmonic distortion TRIG trigger signal TTL transistor transistor logic U UI update interval UISOURCE update interval counter clock signal UPDATE update signal ...

Page 170: ...poration G 7 AT E Series User Manual V V volts VDC volts direct current VIH volts input high VIL volts input low Vin volts in VOH volts output high VOL volts output low Vref reference voltage W WFTRIG waveform generation trigger signal ...

Page 171: ...able 4 10 AT MIO 16XE 10 and AT AI 16XE 10 table 4 12 AT MIO 16XE 50 table 4 13 description table 4 5 differential connections for floating signal sources 4 22 AISENSE signal analog input connections 4 15 AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 8 AT MIO 16E 10 and AT MIO 16DE 10 table 4 10 AT MIO 16XE 10 and AT AI 16XE 10 table 4 12 AT MIO 16XE 50 table 4 13 description table 4 5 AISENS...

Page 172: ...fications AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 A 5 dynamic characteristics A 7 output characteristics A 5 stability A 7 transfer characteristics A 6 voltage output A 7 AT MIO 16E 10 and AT MIO 16DE 10 dynamic characteristics A 16 output characteristics A 14 stability A 16 transfer characteristics A 15 voltage output A 15 AT MIO 16XE 10 dynamic characteristics A 25 output characteristics A 24...

Page 173: ...d wiring considerations 4 55 optional equipment 1 5 calibration adjusting for gain error 5 3 external calibration 5 2 loading calibration constants 5 1 self calibration 5 2 charge injection 3 12 clocks board and RTSI 3 20 commonly asked questions See questions about AT E series boards common mode signal rejection 4 26 configuration See also input configurations base I O address selection 2 3 bus i...

Page 174: ... O connections 4 28 digital timing connections 4 30 diagnostic resources D 1 DIFF differential input mode definition table 3 7 description 4 20 ground referenced signal sources 4 21 nonreferenced or floating signal sources 4 22 single ended connections 4 24 floating signal sources RSE 4 25 grounded signal sources NRSE 4 25 when to use 4 20 digital I O common questions about C 7 operation 3 18 sign...

Page 175: ...pment optional 1 5 example code D 1 EXTREF signal analog output reference connections 4 27 analog output reference selection 3 13 AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 8 AT MIO 16E 10 and AT MIO 16DE 10 table 4 10 description table 4 5 EXTSTROBE signal AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 8 AT MIO 16E 10 and AT MIO 16DE 10 table 4 10 AT MIO 16XE 10 and AT AI 16XE 10 tabl...

Page 176: ...2 AT MIO 16XE 50 table 4 14 description table 4 7 waveform generation timing connections 4 48 GPCTR1_SOURCE signal 4 47 GPCTR1_UP_DOWN signal 4 48 ground referenced signal sources description 4 17 differential connections 4 21 single ended connections NRSE configuration 4 25 H hardware installation 2 1 hardware overview analog input considerations for selecting input ranges 3 10 dither 3 10 input ...

Page 177: ...ingle ended connections 4 24 floating signal sources RSE configuration 4 25 grounded signal sources NRSE configuration 4 25 input polarity and range AT MIO 16E 1 AT MIO 16E 2 AT MIO 643 3 AT MIO 16E 10 and AT MIO 16DE 10 3 7 actual range and measurement precision table 3 8 AT MIO 16XE 10 AT AI 16XE 10 and AT MIO 16XE 50 3 8 AT MIO 16XE 10 AT MIO 16XE 50 actual range and measurement precision table...

Page 178: ... AT MIO 16E 10 and AT MIO 16DE 10 table 4 10 description table 4 6 PB 0 7 signal AT MIO 16E 10 and AT MIO 16DE 10 table 4 10 description table 4 6 PC 0 7 signal table 4 6 PFI0 TRIG1 signal AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 8 AT MIO 16E 10 and AT MIO 16DE 10 table 4 10 AT MIO 16XE 10 and AT AI 16XE 10 table 4 12 AT MIO 16XE 50 table 4 14 description table 4 6 PFI1 TRIG2 signal AT M...

Page 179: ...ignal AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 9 AT MIO 16E 10 and AT MIO 16DE 10 table 4 11 AT MIO 16XE 10 and AT AI 16XE 10 table 4 13 AT MIO 16XE 50 table 4 14 description table 4 7 PFI9 GPCTR0_GATE signal AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 9 AT MIO 16E 10 and AT MIO 16DE 10 table 4 11 AT MIO 16XE 10 and AT AI 16XE 10 table 4 13 AT MIO 16XE 50 table 4 14 description ta...

Page 180: ...mentation xiii RSE referenced single ended input description table 3 7 single ended connections for floating signal sources 4 25 RTSI clocks 3 20 RTSI triggers overview 3 20 specifications AT MIO 16E 1 AT MIO 16E 2and AT MIO 64E 3 A 10 AT MIO 16E 10 and AT MIO 16DE 10 A 18 AT MIO 16XE 10 and AT AI 16XE 10 A 27 AT MIO 16XE 50 A 36 S SCANCLK signal AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 ...

Page 181: ... signal 4 48 GPCTR1_SOURCE signal 4 47 GPCTR1_UP_DOWN signal 4 48 programmable function input connections 4 31 waveform generation timing connections 4 41 UISOURCE signal 4 44 UPDATE signal 4 42 WFTRIG signal 4 41 types of signal sources 4 17 floating 4 17 ground referenced 4 17 single ended connections description 4 24 floating signal sources RSE 4 25 grounded signal sources NRSE 4 25 when to use...

Page 182: ...tability A 25 transfer characteristics A 24 voltage output A 25 bus interface A 28 digital I O A 25 physical A 28 power requirements A 28 timing I O A 26 triggers analog trigger A 27 digital trigger A 27 RTSI A 27 AT MIO 16XE 50 analog input amplifier characteristics A 31 dynamic characteristics A 32 input characteristics A 30 transfer characteristics A 31 analog output dynamic characteristics A 3...

Page 183: ...50 GPCTR0_GATE signal 4 45 GPCTR0_OUT signal 4 46 GPCTR0_SOURCE signal 4 44 GPCTR0_UP_DOWN signal 4 46 GPCTR1_GATE signal 4 47 GPCTR1_OUT signal 4 48 GPCTR1_SOURCE signal 4 47 GPCTR1_UP_DOWN signal 4 48 programmable function input connections 4 31 waveform generation timing connections UNISOURCE signal 4 44 UPDATE signal 4 42 WFTRIG signal 4 41 timing I O specifications AT MIO 16E 1 AT MIO 16E 2 a...

Page 184: ...6DE 10 3 7 AT MIO 16XE 10 AT AI 16XE 10 and AT MIO 16XE 50 3 8 mixing bipolar and unipolar channels note 3 9 unipolar output 3 13 unpacking AT E series boards 1 6 UPDATE signal timing connections 4 42 V VCC signal AT MIO 16E 1 AT MIO 16E 2 and AT MIO 64E 3 table 4 8 AT MIO 16E 10 and AT MIO 16DE 10 table 4 10 AT MIO 16XE 10 and AT AI 16XE 10 table 4 12 AT MIO 16XE 50 table 4 14 voltage output AT M...

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