CHAPTER 3
CHAPTER 3
CHAPTER 3
CHAPTER 3
CHAPTER 3
AWARD
AWARD
AWARD
AWARD
AWARD
®
BIOS SETUP
BIOS SETUP
BIOS SETUP
BIOS SETUP
BIOS SETUP
3-17
Enhanced Memory Write
This item allows you to enable/disable the enhanced memory write.
This function must be disabled if using 512K cache size and TAG address is
set to 8 bits. The settings are Enabled or Disabled.
Read Prefetch Memory RD
Chipset has a prefetch buffer. It will prefetch the DRAM data of
next address in buffer. Then when next access hits this address, CPU can
get the data from this buffer instead of DRAM. It will shorten the cycle time.
The settings are Enabled or Disabled.
CPU to PCI Burst Mem. WR
Select enabled permits PCI burst memory write cycles, for faster
performance. When disabled, performance is slightly slower, but more
reliable. The settings are 3T or 2T.
AGP Aperture Size
This option determines the effective size of the graphics aperture
used in the particular PAC configuration. The AGP aperture is memory-
mapped, while graphics data structure can reside in a graphics aperture. The
aperture range should be programmed as not cacheable in the processor
cache, accesses with the aperture range are forwarded to the main memory,
then PAC will translate the original issued address via a translation table
that is maintained on the main memory. The option allows the selection of
an aperture size of 4MB, 8MB, 16MB, 32MB, 64MB, 128MB, and 256MB.
Summary of Contents for Baby AT SI19
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Page 4: ...Chapter 1 Introduction 1 1 iv ...
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