CHAPTER 3
CHAPTER 3
CHAPTER 3
CHAPTER 3
CHAPTER 3
AWARD
AWARD
AWARD
AWARD
AWARD
®
BIOS SETUP
BIOS SETUP
BIOS SETUP
BIOS SETUP
BIOS SETUP
3-16
SDRAM CAS Latency
This item allows you to select the SDRAM Latency Time. The
setting are 2T or 3T.
SDRAM WR Retire Rate
Chipset has a post write buffer. The buffer will store the data of all
CPU write cycle first, and then forward the data to DRAM. “Retire rate” is
the speed of buffer to DRAM. The settings are X-1-1-1 or X-2-2-2.
SDRAM Wait State Control
This item allows you to select SDRAM wait state control function
during Precharge command. The settings are 1WS or 0WS.
RAMW# Assertion Timing
This item allows you to select the RAMW# assertion timing.
RAMW# is internal DRAM control signal of chipset. The settings are 3T or
2T.
CAS Precharge Time (EDO)
This item allows you to select CAS precharge time for EDO RAM.
The settings are 1T, 1T/2T, or 2T.
CAS Precharge Time (FP)
This item allows you to select CAS precharge time for FP RAM.
The settings are 1T, 1T/2T, or 2T.
CAS # Pulse Width (EDO)
Determines number of CPU clock cycles the CAS signal pulses
during EDO DRAM reads and writes, when memory is not interleaved. The
settings are 2T or 1T.
CAS # Pulse Width (FP)
Determines the number of CPU clock cycles allocated for the CAS
to accumulate its charge before Fast Page mode DRAM is allowed to
precharge. If insufficient time is allowed, refresh may be incomplete and data
may be lost. The settings are 2T or 1T.
Summary of Contents for Baby AT SI19
Page 1: ...Version 1 1 i ...
Page 4: ...Chapter 1 Introduction 1 1 iv ...
Page 8: ...viii ...