Block Diagram
http://www.motorola.com/computer/literature
3-15
3
SCSIP
∗
SCSI present. If set, there is no on-board SCSI interface. If
cleared, on-board SCSI is supported.
P2 Signal Multiplexing
Due to the limited supply of available pins in the P2 backplane connectors
of MVME2603/2604 models that are configured for MVME761 I/O mode,
certain signals are multiplexed through VMEbus connector P2 for
additional I/O capacity.
The signals affected are synchronous I/O control signals that pass between
the base board and the MVME761 transition module. The multiplexing is
a hardware function that is entirely transparent to software.
Four signals are involved in the P2 multiplexing function: MXDO, MXDI,
MXCLK, and MXSYNC
∗
.
MXDO is a time-multiplexed data output line from the main board and
MXDI is a time-multiplexed line from the MVME761 module. MXCLK
is a 10 MHz bit clock for the MXDO and MXDI data lines. MXSYNC
∗
is
asserted for one bit time at time slot 15 (
Table 3-2
) by the
MVME2603/2604 base board. The MVME761 transition module uses
MXSYNC
∗
to synchronize with the base board.
A 16-to-1 multiplexing scheme is used with MXCLK’s 10 MHz bit rate.
16 time slots are defined and allocated as follows:
Table 3-2. P2 Multiplexing Sequence
MXDO (From Base Board)
MXDI (From MVME761)
Time Slot
Signal Name
Time Slot
Signal Name
0
RTS3
0
CTS3
1
DTR3
1
DSR3/MID1
2
LLB3/MODSEL
2
DCD3
3
RLB3
3
TM3/MID0
4
RTS4
4
RI3
5
DTR4
5
CTS4
6
LLB4
6
DSR4/MID3