Motorola MVME2301, Installation And Use Manual

Page: 104 / 167

ENV - Set Environment
6-12
6
ROM Next Access Length (0 - 15) = 0?
The value programmed into theÒROMNALÓ Þeld (Memory
Control ConÞguration Register 8: bits 28-31) to represent wait
states in access time for nibble (or burst) mode ROM accesses.
The lowest allowable ROMNAL setting is $0; the highest
allowable is $F. The value to enter depends on processor speed;
refer to Chapter 1 or Appendix B for appropriate values. The
default value varies according to the systemÕs bus clock speed.
Note ROM Next Access Length is not applicable to the
MVME2300. The configured value is ignored by
PPCBug.
DRAM Parity Enable [On-Detection/Always/Never - O/A/N] = O?
Note This parameter (above) also applies to enabling ECC
for DRAM.
L2 Cache Parity Enable [On-Detection/Always/Never - O/A/N] = O?
PCI Interrupts Route Control Registers (PIRQ0/1/2/3) = 0A0B0E0F?
Initializes the PIRQx (PCI Interrupts) route control registers in
the IBC (PCI/ISA bus bridge controller). The
ENV parameter is
a 32-bit value that is divided by 4 to yield the values for route
control registers PIRQ0/1/2/3. The default is determined by
system type. For details on PCI/ISA interrupt assignments and
for suggested values to enter for this parameter, refer to the
8259
Interrupts section of Chapter 5 in the MVME2300-Series VME
Processor Module ProgrammerÕs Reference Guide .
O
DRAM parity is enabled upon detection. (Default)
A
DRAM parity is always enabled.
N
DRAM parity is never enabled.
O
L2 Cache parity is enabled upon detection. (Default)
A
L2 Cache parity is always enabled.
N
L2 Cache parity is never enabled.