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Glossary

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little-endian

A byte-ordering method in memory where the address

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a word corresponds to the least significant byte. In an
addressed memory word, the bytes are ordered (left to
right) 3, 2, 1, 0, with 3 being the most significant byte.

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ultiplexed

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MCA (bus)

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MPC

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ultimedia

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MPC105

The PowerPC-to-PCI bus bridge chip developed by
Motorola for the Ultra 603/Ultra 604 system board. It
provides the necessary interface between the MPC603/
MPC604 processor and the Boot ROM (secondary cache),
the DRAM (system memory array), and the PCI bus.

MPC601

MotorolaÕs component designation for the PowerPC 601
microprocessor.

MPC603

MotorolaÕs component designation for the PowerPC 603
microprocessor.

MPC604

MotorolaÕs component designation for the PowerPC 604
microprocessor.

MPIC

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reliability as expressed in power on hours (poh). It was
originally developed for the military and can be calculated

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Summary of Contents for MVME2301

Page 1: ...MVME2300 Series VME Processor Module Installation and Use V2300A IH2 ...

Page 2: ...rior written permission of Motorola Inc It is possible that this publication may contain reference to or information about Motorola products machines and programs programming or services that are not announced in your country Such references or information must not be construed to mean that Motorola intends to announce such Motorola products programming or services in your country Restricted Right...

Page 3: ...ation about using the front panel a functional description information about programming the board using the PPCBug debugging Þrmware and advanced debugger topics Other appendices provide the MVME2300 series speciÞcations connector pin assignments and a glossary of terms Additional manuals you may wish to obtain are listed in Appendix A Ordering Related Documentation The information in this manual...

Page 4: ... following the signal name for signals which are edge significant denotes that the actions initiated by that signal occur on high to low transition In this manual assertion and negation are used to specify forcing a signal to a particular state In particular assertion and assert refer to a signal that is active or true negation and negate indicate a signal that is inactive or false These terms are...

Page 5: ...l or other qualiÞed maintenance personnel may remove equipment covers for internal subassembly or component replacement or any internal adjustment Do not replace components with power cable connected Under certain conditions dangerous voltages may exist even with the power cable removed To avoid injuries always disconnect power and discharge circuits before touching them Do Not Service or Adjust A...

Page 6: ...tation are copyrighted materials Making unauthorized copies is prohibited by law No part of the software or documentation may be reproduced transmitted transcribed stored in a retrieval system or translated into any language or computer language in any form or by any means without the prior written permission of Motorola Inc European Notice Board products with the CE marking comply with the EMC Di...

Page 7: ...rk of International Business Machines Corporation and is used by Motorola with permission All other products mentioned in this document are trademarks or registered trademarks of their respective holders Copyright Motorola 1998 All Rights Reserved Printed in the United States of America April 1998 ...

Page 8: ......

Page 9: ... Hardware 1 7 MVME230x 1 7 Setting the Flash Memory Bank A Bank B Reset Vector Header J15 1 10 Setting the VMEbus System Controller Selection Header J16 1 10 Setting the General Purpose Software Readable Header J17 1 11 PMCs 1 12 PMCspan 1 12 System Console Terminal 1 12 Installing the MVME230x Hardware 1 13 Taking ESD Precautions 1 13 PMCs 1 13 Primary PMCspan 1 15 Secondary PMCspan 1 18 MVME230x...

Page 10: ...603 604 Processor 3 3 PCI Bus Latency 3 5 DRAM Memory 3 7 DRAM Latency 3 8 Flash Memory 3 11 Flash Latency 3 12 Ethernet Interface 3 12 PCI Mezzanine Card PMC Interface 3 13 PMC Slot 1 Single Width PMC 3 14 PMC Slot 2 Single Width PMC 3 14 PMC Slots 1 and 2 Double Width PMC 3 15 PCI Expansion 3 15 VMEbus Interface 3 15 Asynchronous Debug Port 3 16 PCI ISA Bridge PIB Controller 3 16 Real Time Clock...

Page 11: ...Endian Issues 4 10 Processor Memory Domain 4 10 PCI Domain 4 10 VMEbus Domain 4 11 Chapter 5 PPCBug PPCBug Overview 5 1 PPCBug Basics 5 1 Memory Requirements 5 3 PPCBug Implementation 5 3 MPU Hardware and Firmware Initialization 5 3 Using PPCBug 5 5 Debugger Commands 5 6 Diagnostic Tests 5 10 Chapter 6 Modifying the Environment Overview 6 1 CNFG ConÞgure Board Information Block 6 2 ENV Set Environ...

Page 12: ...ents C 1 VMEbus Connector P1 C 2 VMEbus Connector P2 C 4 Serial Port Connector DEBUG J2 C 6 Ethernet Connector 10BASET J3 C 6 CPU Debug Connector J1 C 7 PCI Expansion Connector J18 C 12 PCI Mezzanine Card Connectors J11 through J14 C 15 PCI Mezzanine Card Connectors J21 through J24 C 18 Solving Startup Problems D 1 Abbreviations Acronyms and Terms to Know GL 1 ...

Page 13: ...Module Placement on MVME230x 1 15 Figure 1 4 PMCspan 002 Installation on an MVME230x 1 17 Figure 1 5 PMCspan 010 Installation onto a PMCspan 002 MVME230x 1 19 Figure 2 1 MVME230x DEBUG Port ConÞguration 2 5 Figure 3 1 MVME230x Block Diagram 3 4 Figure 3 2 Memory Block Diagram 3 8 Figure 4 1 VMEbus Master Mapping 4 5 Figure 4 2 MVME230x Interrupt Architecture 4 7 ...

Page 14: ...xiv ...

Page 15: ... Default View of the Memory Map 4 2 Table 4 2 PCI Arbitration Assignments 4 6 Table 4 3 Classes of Reset and Effectiveness 4 9 Table 5 1 Debugger Commands 5 7 Table 5 2 Diagnostic Test Groups 5 11 Table A 1 Motorola Computer Group Documents A 1 Table A 2 ManufacturersÕ Documents A 2 Table A 3 Related SpeciÞcations A 5 Table B 1 MVME230x SpeciÞcations B 1 Table C 1 P1 VMEbus Connector Pin Assignmen...

Page 16: ...C 8 J13 J14 PMC1 Connector Pin Assignments C 16 Table C 9 J21 and J22 PMC2 Connector Pin Assignments C 18 Table C 10 J23 and J24 PMC2 Connector Pin Assignments C 19 Table D 1 Troubleshooting MVME230x Modules D 2 ...

Page 17: ... Two front panel cutouts provide access to PMC I O One double width or two single width PMCs can be installed directly on the MVME230x Optionally one or two PMCspan PCI expansion mezzanine modules can be added to provide the capability of up to four additional PMC modules Two RJ45 connectors on the front panel provide the interface to 10 100Base T Ethernet and to a debug serial port The following ...

Page 18: ...to two PMCs It occupies a single VMEmodule slot except when optional PCI expansion mezzanine modules are also used The MVME230x interfaces to the VMEbus via the P1 and P2 connectors It also draws 5V 12V and 12V power from the VMEbus backplane through these two connectors The 3 3V power used for the PCI bridge chip and possibly for the PMC mezzanine is derived onboard from the 5V power Support for ...

Page 19: ...0x PCI Mezzanine Cards PMCs The PMC slots on the MVME230x board are IEEE P1386 1 compliant P2 I O based PMCs that follow the PMC committee recommendation for PCI I O when using the 5 row VME64 extension connector will be pin out compatible with the MVME230x The MVME230x board supports both front panel I O and rear panel P2 I O through either PMC slot 1 or PMC slot 2 64 pins of I O from slot 1 and ...

Page 20: ...onnector is provided on the front panel of the MVME230x for this purpose Overview of Start Up Procedures The following table lists the things you will need to do before you can use this board and tells where to find the information you need to perform each step Be sure to read this entire chapter and read all Caution and Warning notes before beginning Table 1 3 Start Up Overview What you need to d...

Page 21: ...Cs refer to the PMC manuals provided with these cards Install the primary PMCspan module if used Primary PMCspan 1 17 For additional information on PMCspan refer to the PMCspan PMC Adapter Carrier Module Installation and Use manual listed in Appendix A Ordering Related Documentation A 1 Install the secondary PMCspan module if used Secondary PMCspan 1 19 For additional information on PMCspan refer ...

Page 22: ...ndix A Ordering Related Documentation A 1 Examine the environmental parameters and make any changes needed ENV Set Environment 6 3 You may also wish to obtain the PPCBug Firmware Package UserÕs Manual listed in Appendix A Ordering Related Documentation A 1 Program the MVME230x module and PMCs as needed for your applications Preparing the MVME230x Hardware 1 7 Programming the MVME230x 4 1 For addit...

Page 23: ...the desired configuration and ensure proper operation of the MVME230x you may need to carry out certain modifications before and after installing the modules The following paragraphs discuss the preparation of the MVME230x hardware components prior to installing them into a chassis and connecting them MVME230x The MVME230x provides software control over most options by setting bits in control regi...

Page 24: ...s the placement of the switches jumper headers connectors and LED indicators on the MVME230x Manually configurable items on the MVME230x include Flash memory bank A bank B reset vector J15 VMEbus system controller selection header J16 General purpose software readable header J17 The MVME230x has been factory tested and is shipped with the configurations described in the following sections The MVME...

Page 25: ...BASET 1 J16 J17 16 15 2 1 J11 SOFTWARE READEABLE HEADER J22 J21 J1 ETHERNET PORT J3 ABORT SWITCH RESET SWITCH DS 1 S1 S2 VME BUS PCI MEZZANINE CARD PCI MEZZANINE CARD J24 J23 J14 J13 J18 3 DEBUG PORT J2 DS 2 DS 3 DS 4 1 2 113 114 1 2 64 63 1 2 64 63 1 2 64 63 1 2 64 63 1 2 64 63 1 2 64 63 1 2 64 63 1 2 64 63 1 2 189 190 DEBUG CPU BFL PMC PMC 2 PMC1 3 1 J15 XU2 XU1 FLASH SOCKETS ...

Page 26: ... and 2 for Bank A factory configuration or between J15 pins 2 and 3 for Bank B When the jumper is installed the Falcon chipset maps 0xFFF00100 to the Bank B sockets Setting the VMEbus System Controller Selection Header J16 The MVME230x is factory configured in automatic system controller mode i e a jumper is installed across pins 2 and 3 of header J16 This means that the MVME230x determines if it ...

Page 27: ...shipped from the factory with J17 set to all 0s jumpers on all pins as shown in Figure 1 2 The PowerPC firmware PPCBug reserves all bits SRH0 to SRH7 With the jumper installed between pins 3 and 4 factory configuration the debugger uses the current user setup operation parameters in Flash When the jumper is removed making the bit a 1 the debugger uses the default setup operation parameters in NVRA...

Page 28: ...tllation and Use manual for instructions System Console Terminal Ensure that jumpers are installed on all bits on header J17 of the MVME230x board as shown in Figure 1 2 This is necessary when the PPCBug firmware is used Connect the terminal via a cable to the RJ45 DEBUG connector J2 See Table C 3 for pin signal assignments Set up the terminal as follows J17 15 Bit 0 SRH0 Bit 1 SRH1 Bit 2 SRH2 Bit...

Page 29: ...m Electronic components such as disk drives computer boards and memory modules can be extremely sensitive to Electro Static Discharge ESD After removing the component from the system or its protective wrapper place the component flat on a grounded static free surface and in the case of a board component side up Do not slide the component over any surface If an ESD station is not available you can ...

Page 30: ...ution Inserting or removing modules with power applied may result in damage to module components Warning Dangerous voltages capable of causing death are present in this equipment Use extreme caution when handling testing and adjusting 3 If the MVME230x has already been installed in a VMEbus card slot carefully remove it Lay the MVME230x flat with connectors P1 and P2 facing you Caution Avoid touch...

Page 31: ...ectors for a single width PMC J11 J12 J13 J14 or J21 J22 J23 J24 all eight for a double width PMC on the MVME230x 6 Insert the two short Phillips screws through the holes at the forward corners of the PMC module into the standoffs on the MVME230x Tighten the screws 7 If installing two single width PMCs repeat the above procedure for the second PMC Primary PMCspan To install a PMCspan 002 PCI expan...

Page 32: ...own Turn the AC or DC power off and remove the AC cord or DC power lines from the system Remove chassis or system cover s as necessary for access to the VME module card cage Caution Inserting or removing modules with power applied may result in damage to module components Warning Dangerous voltages capable of causing death are present in this equipment Use extreme caution when handling testing and...

Page 33: ...Installing the MVME230x Hardware 1 17 1 Figure 1 4 PMCspan 002 Installation on an MVME230x 2081 9708 P4 J18 ...

Page 34: ...e corners of the PMCspan and into the standoffs on the MVME230x module Tighten the screws Note The screws have two different head diameters Use the screws with the smaller heads on the standoffs next to VMEbus connectors P1 and P2 Secondary PMCspan The PMCspan 010 PCI expansion module mounts on top of a PMCspan 002 PCI expansion module To install a PMCspan 010 on your MVME230x refer to Figure 1 5 ...

Page 35: ...Installing the MVME230x Hardware 1 19 1 Figure 1 5 PMCspan 010 Installation onto a PMCspan 002 MVME230x 2065 9708 P3 J3 ...

Page 36: ... it flat with the P1 and P2 connectors facing you Caution Avoid touching areas of integrated circuitry static discharge can damage these circuits 4 Remove the four short Phillips screws from the standoffs in each corner of the primary PCI expansion module PMCspan 002 5 Attach the four standoffs to the PMCspan 002 6 Place the PMCspan 010 on top of the PMCspan 002 Align the mounting holes in each co...

Page 37: ...out the procedure 2 Perform an operating system shutdown a Turn the AC or DC power off and remove the AC cord or DC power lines from the system Caution Inserting or removing modules with power applied may result in damage to module components Warning Dangerous voltages capable of causing death are present in this equipment Use extreme caution when handling testing and adjusting b Remove chassis or...

Page 38: ... connectors on the backplane Do not damage or bend connector pins 5 Secure the MVME230x and PMCspans if used in the chassis with the screws provided making good contact with the transverse mounting rails to minimize RF emissions Note Some VME backplanes e g those used in Motorola ÒModular ChassisÓ systems have an auto jumpering feature for automatic propagation of the IACK and BG signals Step 6 do...

Page 39: ...2 D32 However it handles A16 or A24 devices in the address ranges indicated in Chapter 4 D8 and or D16 devices in the system must be handled by the PowerPC processor software Refer to the memory maps in Chapter 4 The MVME230x contains shared onboard DRAM whose base address is software selectable Both the onboard processor and off board VMEbus devices see this local DRAM at base physical address 00...

Page 40: ...ME230x In general hardware multiprocessor features are supported Other MPUs on the VMEbus can interrupt disable communicate with and determine the operational status of the processor s One register of the Universe set includes four bits that function as location monitors to allow one MVME230x processor to broadcast a signal to any other MVME230x processors All eight registers are accessible from a...

Page 41: ...cess is performed by the PPCBug firmware power up or system reset The firmware initializes the devices on the MVME230x module in preparation for booting the operating system The firmware is shipped from the factory with an appropriate set of defaults In most cases there is no need to modify the firmware configuration before you boot the operating system Refer to Chapter 6 for further information a...

Page 42: ...g diode status indicators BFL CPU PMC two located on the MVME230x front panel STARTUP INITIALIZATION MONITOR BOOTING POST Power up reset initialization Initialize devices on the MVME230x Power On Self Test diagnostics Firmware configured boot mechanism Interactive command driven on line PowerPC debugger when terminal connected if so configured Default is no boot module system ...

Page 43: ...ME230x VME processor module is the system controller The Universe ASIC includes both a global and a local reset driver When the Universe operates as the VMEbus system controller the reset driver provides a global system reset by asserting the VMEbus signal SYSRESET A SYSRESET signal may be generated by the RESET switch a power up reset a watchdog timeout or by a control bit in the Miscellaneous Co...

Page 44: ...ED indicates PCI activity lights when the PCI bus grant to PMC2 signal line on the PCI bus is active This indicates that a PMC installed on slot 2 is active PMC DS4 The bottom green PMC LED indicates PCI activity lights when the PCI bus grant to PMC1 signal line on the PCI bus is active This indicates that a PMC installed on slot 1 is active 10 100 BASET Port The RJ45 port on the front panel of th...

Page 45: ...nnecting a terminal to the MVME230x to serve as the firmware console for the factory installed debugger PPCBug The port is configured as follows 8 bits per character 1 stop bit per character Parity disabled no parity Baud rate 9600 baud default baud rate at power up After power up the baud rate of the DEBUG port can be reconfigured by using the debuggerÕs Port Format PF command Refer to Chapters 5...

Page 46: ...the userÕs manual for the particular PMC PCI MEZZANINE CARD PMC Slot 1 The right most lower opening labeled PCI MEZZANINE CARD on the MVME230x front panel provides front panel I O access to a PMC that is connected to the 64 pin connectors J11 through J14 on the MVME230x module Connector J14 allows rear panel P2 I O This slot is MVME230x Port 1 PCI MEZZANINE CARD PMC Slot 2 The left most upper open...

Page 47: ...specific I O It also has a P1 connector and a 5 row P2 connector for power and VMEbus I O The PMCspan has two green LEDs on its front panel one for each PMC slot labeled PMC2 and PMC1 Both LEDs are illuminated during reset An individual LED is illuminated whenever a PMC has been granted bus mastership of the secondary PCI bus The right most lower opening labeled PCI MEZZANINE CARD on the front pan...

Page 48: ...Operating Instructions 2 8 2 ...

Page 49: ...merÕs Reference Guide part number V2300A PG Refer to it for a functional description of the MVME230x in greater depth Features The following table summarizes the features of the MVME230x VME processor module Table 3 1 MVME230x Features Feature Description Microprocessor 200 MHZ MPC603 PowerPCTM processor MVME2301 2304 models 300 MHZ MPC604 PowerPCTM processor MVME2305 2308 models Form factor 6U VM...

Page 50: ...hernet I O 10Base T 100Base TX connections via RJ45 connector on front panel PCI interface Two IEEE P1386 1 PCI Mezzanine Card PMC slots for one double width or two single width PMCs Front panel and or VMEbus P2 I O on both PMC slots One 114 pin Mictor connector for optional PMCspan expansion module VMEbus interface VMEbus system controller functions VME64 extension VMEbus to local bus interface A...

Page 51: ...nterface from the Processor Bus to PCI A W83C553 PCI ISA Bridge PIB Controller device performs the bridge function between PCI and ISA The Universe ASIC device provides the interface between the PCI Local Bus and the VMEbus A Falcon chipset is the ECC memory controller The Peripheral Component Interface PCI local bus is a key feature In addition to the on board local bus peripherals the PCI bus su...

Page 52: ...H 3MB or 5MB PHB MPIC RAVEN ASIC MEMORY CONTROLLER FALCON CHIPSET 64 BIT PMC SLOT PCI EXPANSION 33MHz 32 64 BIT PCI LOCAL BUS PIB W83C553 VME BRIDGE UNIVERSE BUFFERS VME P2 VME P1 RTC NVRAM WD MK48T59 559 ETHERNET DEC21140 10BT 100BTX FRONT PANEL ISA BUS 66MHz MPC604 PROCESSOR BUS DRAM 16 32 64 128MB PMC FRONT I O SLOT SERIAL PORT PC16550 UART ISA REGISTERS ...

Page 53: ...essing between the PowerPC microprocessor bus and the PCI local bus The power requirements for the MVME230x are shown in Table 3 2 PCI Bus Latency Writes to PCI can be posted The read access latency for PCI bound cycles initialted by the MPMC60x bus master consists of the following components Tstart Start up time TS to PCI bus Request Tstart is 6 system clocks Tarb PCI bus arbitration time Tac PCI...

Page 54: ...d to be 6 system clocks 3 PCI clocks Medium DEVSEL target zero wait PCI timing The following table shows the ECC memory access latency for PCI initiated cycles Table 3 3 PowerPC 60x Bus to PCI Access Timing Access Type System Clock Periods Required For Total Clocks 1st Beat 2nd Beat 3rd Beat 4th Beat 4 Beat Read 64 bit PCI Target 27 1 1 1 30 4 Beat Read 32 bit PCI Target 35 1 1 1 38 4 Beat Write 6...

Page 55: ...ry size can be 16MB 32MB 64MB or 128MB The DRAM blocks are controlled by the Falcon chipset which performs two way interleaving and provides single bit error correction and double bit error correction ECC is calculated over 72 bits Table 3 4 PCI to ECC Memory Access Timing Access Type PCI Clock Periods Required for Maximum Bandwidth 1st Beat 2nd Beat 3rd Beat nth Beat 64 bit Burst Reads 10 1 1 1 6...

Page 56: ... A and Block B to the Falcon chipset Refer to the MVME2300 Series VME Processor Module ProgrammerÕs Reference Guide for additional information and programming details The block diagram for the memory interface is shown in the following figure Figure 3 2 Memory Block Diagram DRAM Latency The ECC memory access latency times for 60ns fast page DRAMs are shown in the following table Address Control Da...

Page 57: ...s Timing using 60ns Page Devices Access Type Clock Periods Required for Total Clocks 1st Beat 2nd Beat 3rd Beat 4th Beat 4 Beat Read after Idle Quad word aligned 9 1 2 1 13 4 Beat Read after Idle Quad word misaligned 9 3 1 1 14 4 Beat Read after 4 Beat Read Quad word aligned 7 3 1 1 2 1 11 7 4 Beat Read after 4 Beat Read misaligned 6 2 1 3 1 1 11 7 4 Beat Write after Idle 4 1 1 1 7 4 Beat Write af...

Page 58: ...er or shorter Table 3 6 PowerPC 60x Bus to DRAM Access Timing Using 50ns EDO Devices Access Type Clock Periods Required for Total Clocks 1st Beat 2nd Beat 3rd Beat 4th Beat 4 Beat Read after Idle Quad word aligned 8 1 1 1 11 4 Beat Read after Idle Quad word misaligned 8 2 1 1 12 4 Beat Read after 4 Beat Read Quad word aligned 5 2 1 1 1 1 8 5 4 Beat Read after 4 Beat Read misaligned 4 2 1 2 1 1 8 6...

Page 59: ...etween J15 pins 2 and 3 for Bank B When the jumper is installed the Falcon chipset maps 0xFFF00100 to the Bank B sockets The onboard monitor debugger PPCBug resides in the Flash chips PPCBug provides functionality for Booting the system Initializing after a reset Displaying and modifying configuration variables Running self tests and diagnostics Updating firmware ROM Under normal operation the Fla...

Page 60: ...ess is 08003E2xxxxx where xxxxx is the unique 5 nibble number assigned to the board i e every board has a different value for xxxxx Each MVME230x displays its Ethernet station address on a label attached to the base board in the PMC connector keepout area just behind the front panel In addition the six bytes including the Ethernet station address are stored in the NVRAM BBRAM configuration area sp...

Page 61: ...efer to the BBRAM TOD Clock memory map description in the MVME2300 Series VME Processor Module Programmer s Reference Guide for detailed programming information PCI Mezzanine Card PMC Interface A key feature of the MVME230x family is the PCI bus In addition to the on board local bus devices Ethernet etc the PCI bus supports an industry standard mezzanine interface IEEE P1386 1 PCI Mezzanine Card P...

Page 62: ...lot 1 Single Width PMC PMC slot 1 has the following characteristics For P2 I O configurations all I O pins of PMC slot 1 are routed to the 5 row power adapter card Pins 1 through 64 of J14 are routed to row C and row A of P2 PMC Slot 2 Single Width PMC PMC slot 2 has the following characteristics Mezzanine Type PCI Mezzanine Card PMC Mezzanine Size S1B Single width standard depth 75mm x 150mm with...

Page 63: ...Ebus Interface The VMEbus interface is implemented with the CA91C042 Universe ASIC The Universe chip interfaces the 32 64 bit PCI local bus to the VMEbus The Universe ASIC provides The PCI bus to VMEbus interface The VMEbus to PCI bus interface The DMA controller functions of the local VMEbus The Universe chip includes Universe Control and Status Registers UCSRs for interprocessor communications I...

Page 64: ...and 2 5V supplies are regulated onboard from the 5 power Asynchronous Debug Port A National Semiconductor PC16550 Universal Asynchronous Receiver Transmitter UART provides the asynchronous debug port TTL level signals for the port are routed through appropriate EIA 232 D drivers and receivers to an RJ45 connector on the front panel The external signals are ESD protected This serial port can suppor...

Page 65: ...of the CONADD and CONDAT Configuration Address and Data registers in the Raven bridge controller ASIC The registers are located at offsets CF8 and CFC respectively from the PCI I O base address Real Time Clock NVRAM Timer Function The MVME230x employs an SGS Thomson surface mount M48T59 T559 RAM and clock chip to provide 8KB of non volatile static RAM a real time clock and a watchdog timer functio...

Page 66: ...dge The Raven ASIC provides the bridge function between the MPC60x bus and the PCI Local Bus It provides 32 bit addressing and 64 bit data 64 bit addressing dual address cycle is not supported The Raven supports various PowerPC processor external bus frequencies up to 66MHz and PCI frequencies up to 33MHz There are four programmable map decoders for each direction to provide flexible address mappi...

Page 67: ... has a specific function Counter 0 is associated with interrupt request line IRQ0 It can be used for system timing functions such as a timer interrupt for a time of day function Counter 1 generates a refresh request signal for ISA memory This timer is not used in the MVME230x Counter 2 provides the tone for the speaker output function on the PIB controller the SPEAKER_OUT signal which can be cable...

Page 68: ...agram 3 20 3 periodic interrupts For information on programming these timers refer to the data sheet for the W83C553 PIB controller and to the MVME2300 Series VMe P rocessor Module ProgrammerÕs Reference Guide ...

Page 69: ...he PMCs refer to the applicable userÕs manual furnished with the PMCs Memory Maps There are multiple buses on the MVME230x and each bus domain has its own view of the memory map The following sections describe the MVME230x memory organization from the following three points of view The mapping of all resources as viewed by the MPU processor bus memory map The mapping of onboard resources as viewed...

Page 70: ...ble 4 1 defines the entire default map 00000000 to FFFFFFFF Notes The first 1MB of Flash bank A soldered 2MB or 4MB Flash appears in this range after a reset if the rom_b_rv control bit in the FalconÕs ROM B Base Size register is cleared If the rom_b_rv control bit is set this address range maps to Flash bank B socketed 1MB Flash Table 4 1 Processor Default View of the Memory Map Processor Address...

Page 71: ...iled PCI memory maps including suggested CHRP and PREP compatible memory maps refer to the MVME2300 Series VME Processor Module ProgrammerÕs Reference Guide VMEbus Memory Map The VMEbus is programmable Like other parts of the MVME230x memory map the mapping of local resources as viewed by VMEbus masters varies among applications The Universe PCI VME bus bridge ASIC includes a user programmablemapd...

Page 72: ...SIC MPU PCI bus bridge controller Winbond W83C553 PIB PCI ISA bus bridge controller DECchip 21140 Ethernet controller Universe ASIC PCI VME bus bridge controller PMC Slot 1 PCI mezzanine card PMC Slot 2 PCI mezzanine card PCI Expansion Slot The Winbond W83C553 PIB device supplies the PCI arbitration support for these seven types of devices The PIB supports flexible arbitration modes of fixed prior...

Page 73: ...16 PROGRAMMABLE SPACE PCI MEMORY PROCESSOR PCI MEMORY SPACE PCI ISA MEMORY SPACE PCI I O SPACE MPC RESOURCES NOTE 1 NOTE 1 NOTE 2 NOTE 3 ONBOARD MEMORY 1 Programmable mapping done by Raven ASIC 2 Programmable mapping performed via PCI Slave images in Universe ASIC 3 Programmable mapping performed via Special Slave image SLSI in Universe ASIC NOTES ...

Page 74: ...errupts The processor processor self interrupts The Falcon chip set memory error interrupts The PCI bus interrupts from PCI devices The ISA bus interrupts from ISA devices Figure 4 2 illustrates interrupt architecture on the MVME230x For details on interrupt handling refer to the MVME2300 Series VME Processor Module ProgrammerÕs Reference Guide Table 4 2 PCI Arbitration Assignments PCI Bus Request...

Page 75: ...4 Figure 4 2 MVME230x Interrupt Architecture The MVME230x routes the interrupts from the PMCs and PCI expansion slots as follows 11559 00 9609 PIB 8529 Pair Processor INT_ MCP_ RavenMPIC INT SERR_ PERR_ PCI Interrupts ISA Interrupts ...

Page 76: ... 3 Watchdog timer Reset function controlled by the SGS Thomson MK48T59 timekeeper device resets the VMEbus when the MVME230x is system controller 4 ALT_RST function controlled by the Port 92 register in the PIB resets the VMEbus when the MVME230x is system controller 5 PCI ISA I O Reset function controlled by the Clock Divisor register in the PIB RavenMPIC PMC Slot 1 INTA INTB INTC INTD PMC Slot 2...

Page 77: ...cted by the various types of resets For details on using resets refer to the MVME2300 Series VME Processor Module ProgrammerÕs Reference Guide Table 4 3 Classes of Reset and Effectiveness Device Affected Processor Raven ASIC Falcon Chip Set PCI Devices ISA Devices VMEbus as system controller Reset Source Power On reset Reset switch Watchdog reset VME SYSRESET signal VME System SW reset VME Local S...

Page 78: ...rrangement and reordering when running in little endian mode The MPC registers in the Raven MPU PCI bus bridge controller ASIC and the Falcon memory controller chip set as well as DRAM Flash and system registers always appear as big endian Role of the Raven ASIC Because the PCI bus is little endian the Raven performs byte swapping in both directions from PCI to memory and from the processor to PCI...

Page 79: ... byte swapping in both directions from PCI to VMEbus and from VMEbus to PCI to maintain address invariance regardless of the mode of operation in the processorÕs domain VMEbus Domain The VMEbus is inherently big endian All devices connected directly to the VMEbus must operate in big endian mode regardless of the mode of operation in the processorÕs domain In big endian mode byte swapping is perfor...

Page 80: ...Programming the MVME230x 4 12 4 ...

Page 81: ...em calls and other advanced user topics For full user information about PPCbug refer to the PPCBug Firmware Package UserÕs Manual and the PPCBug Diagnostics Manual listed in the Related Documentation appendix PPCBug Basics The PowerPC debug firmware PPCBug is a powerful evaluation and debugging tool for systems built around the Motorola PowerPC microcomputers Facilities are available for loading a...

Page 82: ...nitor that accepts commands from the system console terminal When using PPCBug you operate out of either the debugger directory or the diagnostic directory If you are in the debugger directory the debugger prompt PPC1 Bug is displayed and you have all of the debugger commands at your disposal If you are in the diagnostic directory the diagnostic prompt PPC1 Diag is displayed and you have all of th...

Page 83: ...o socketed 32 pin PLCC Flash devices that together provide 1MB of storage The executable code is checksummed at every power on or reset firmware entry and the result which includes a precalculated checksum contained in the Flash devices is verified against the expected checksum MPU Hardware and Firmware Initialization The debugger performs the MPU hardware and firmware initialization process This ...

Page 84: ...m NVRAM 15 Initializes the read only memory controller with the speed of read only memory 16 Enables the MPU s instruction cache 17 Copies the MPU s exception vector table from FFF00000 to 00000000 18 Verifies MPU type 19 Enables the super scalar feature of the MPU boards with MPC604 type chips only 20 Verifies the external bus clock speed of the MPU 21 Determines the debugger s console host ports...

Page 85: ...ed Default is no Self Test 33 Extinguishes the board fail LED if Self Test passed and outputs any warning messages 34 Executes boot program if so configured Default is no boot 35 Executes the debugger monitor i e issues the PPC1 Bug prompt Using PPCBug PPCBug is command driven it performs its various operations in response to commands that you enter at the keyboard When the PPC1 Bug prompt appears...

Page 86: ...s in the PPCBug Firmware Package UserÕs Manual Chapter 3 A debugger command is made up of the following parts The command name either uppercase or lowercase e g MD or md Any required arguments as specified by command At least one space before the first argument Precede all other arguments with either a space or comma One or more options Precede an option or a string of options with a semicolon If ...

Page 87: ...cess CSAW PCI ConÞguration Space WRITE Access DC Data Conversion DMA Block of Memory Move DS One Line Disassembler DU Dump S Records ECHO Echo String ENV Set Environment FORK Fork Idle MPU at Address FORKWR Fork Idle MPU with Registers GD Go Direct Ignore Breakpoints GEVBOOT Global Environment Variable Boot GEVDEL Global Environment Variable Delete GEVDUMP Global Environment Variable s Dump GEVEDI...

Page 88: ...ro Edit MAL Enable Macro Listing NOMAL Disable Macro Listing MAR Load Macros MAW Save Macros MD MDS Memory Display MENU System Menu MM Memory Modify MMD Memory Map Diagnostic MS Memory Set MW Memory Write NAB Automatic Network Boot NAP Nap MPU NBH Network Boot Operating System Halt NBO Network Boot Operating System NIOC Network I O Control NIOP Network I O Physical NIOT Network I O Teach ConÞgurat...

Page 89: ...d Loop RM Register Modify RS Register Set RUN MPU Execution Status SD Switch Directories SET Set Time and Date SROM SROM Examine Modify SYM Symbol Table Attach NOSYM Symbol Table Detach SYMS Symbol Table Display Search T Trace TA Terminal Attach TIME Display Time and Date TM Transparent Mode TT Trace to Temporary Breakpoint VE Verify S Records Against Memory VER Revision Version Display WL Write L...

Page 90: ... Directories command You may view a list of the commands in the directory that you are currently in by using the HE Help command If you are in the debugger directory the debugger prompt PPC1 Bug displays and all of the debugger commands are available Diagnostics commands cannot be entered at the PPC1 Bug prompt If you are in the diagnostic directory the diagnostic prompt PPC1 Diag displays and all...

Page 91: ...oups Test Group Description CL1283 Parallel Interface CL1283 Tests DEC DEC21x40 Ethernet Controller Tests ISABRDGE PCI ISA Bridge Tests KBD8730x PC8730x Keyboard Mouse Tests L2CACHE Level 2 Cache Tests NCR NCR 53C8xx SCSI 2 I O Processor Tests PAR8730x Parallel Interface PC8730x Test UART Serial Input Output Tests PCIBUS PCI PMC Generic Tests RAM Local RAM Tests RTC MK48Txx Timekeeping Tests SCC S...

Page 92: ...Using PPCBug 5 12 5 ...

Page 93: ...ameters of the hardware Use the PPCBug command CNFG to change those parameters Use the PPCBug command ENV to change configurable PPCBug parameters in NVRAM The CNFG and ENV commands are both described in the PPCBug Firmware Package User s Manual Refer to that manual for general information about their use and capabilities The following paragraphs present additional information about CNFG and ENV t...

Page 94: ... data strings and data strings are right justified The data strings are padded with zeroes if the length is not met The Board Information Block is factory configured before shipment There is no need to modify block parameters unless the NVRAM is corrupted Refer to the MVME2300 Series VME Processor Module ProgrammerÕs Reference Guide for the actual location and other information about the Board Inf...

Page 95: ...d described below are the parameters that you can configure using ENV The default values shown were those in effect when this publication went to print Configuring the PPCBug Parameters The parameters that can be configured using ENV are Bug or System environment B S B Field Service Menu Enable Y N N B Bug is the mode where no system type of support is displayed However system related items are st...

Page 96: ...ster MPCR in shared RAM to pass and start execution of the cross loaded program B Use both the GCSR and the MPCR methods to pass and start execution of the cross loaded program Default N Do not use any Remote Start Method Y Accesses will be made to the appropriate system buses e g VMEbus local MPU bus to determine the presence of supported controllers Default N Accesses will not be made to the VME...

Page 97: ... image from a network interface as from a mass storage device N Do not enable PReP style network booting Default Y Negate the VMEbus SYSFAIL signal during board initialization N Negate the VMEbus SYSFAIL signal after successful completion or entrance into the bug command monitor Default Y Local SCSI bus is reset on debugger setup N Local SCSI bus is not reset on debugger setup Default A Asynchrono...

Page 98: ...topping the boot by use of the BREAK key The time value is from 0 255 seconds Default 5 seconds Auto Boot Enable Y N N Auto Boot at power up only Y N N Y Give boot priority to devices deÞned in the fw boot path global environment variable GEV N Do not give boot priority to devices listed in the fw boot path GEV Default Y Give boot priority to devices deÞned in the fw boot path GEV at power up rese...

Page 99: ...e Autoboot Scan option is enabled If you modify the list follow the format shown above uppercase letters using forward slash as separator Y If Autoboot is enabled the Autoboot process attempts to boot from devices speciÞed in the scan list e g FDISK CDROM TAPE HDISK Default N If Autoboot is enabled the Autoboot process uses the Controller LUN and Device LUN to boot ...

Page 100: ...t Þnds the Þrst ÒbootableÓ partition That is then the partition that will be booted Other acceptable values are 1 2 3 or 4 In these four cases the partition speciÞed will be booted without searching Auto Boot Abort Delay 7 The time in seconds that the Autoboot sequence will delay before starting the boot The purpose for the delay is to allow you the option of stopping the boot by use of the BREAK ...

Page 101: ...Mboot module Default FFF00000 ROM Boot Direct Ending Address FFFFFFFC The last location tested when PPCBug searches for a ROMboot module Default FFFFFFFC Network Auto Boot Enable Y N N Network Auto Boot at power up only Y N N Y ROMboot is attempted at power up only Default N ROMboot is attempted at any reset Y VMEbus address space in addition to the usual areas of memory will be searched for a ROM...

Page 102: ...M 00001000 The address where the network interface conÞguration parameters are to be saved retained in NVRAM these parameters are the necessary parameters to perform an unattended network boot A typical offset might be 1000 but this value is application speciÞc Default 00001000 Caution If you use the NIOT debugger command these parameters need to be saved somewhere in the offset range 00001000 thr...

Page 103: ...west speed found on the available banks of DRAM memory ROM First Access Length 0 31 10 This is the value programmed into theÒROMFALÓ Þeld Memory Control ConÞguration Register 8 bits 23 27 to indicate the number of clock cycles used in accessing the ROM The lowest allowable ROMFAL setting is 00 the highest allowable is 1F The value to enter depends on processor speed refer to Chapter 1 or Appendix ...

Page 104: ...es to enabling ECC for DRAM L2 Cache Parity Enable On Detection Always Never O A N O PCI Interrupts Route Control Registers PIRQ0 1 2 3 0A0B0E0F Initializes the PIRQx PCI Interrupts route control registers in the IBC PCI ISA bus bridge controller The ENV parameter is a 32 bit value that is divided by 4 to yield the values for route control registers PIRQ0 1 2 3 The default is determined by system ...

Page 105: ...odes is included in the section on MPU Hardware and Firmware Initialization in Chapter 1 of the PPCBug Firmware Package UserÕs Manual Configuring the VMEbus Interface ENV asks the following series of questions to set up the VMEbus interface for the MVME230x modules To perform this configuration you should have a working knowledge of the Universe ASIC as described in your MVME2300 Series VME Proces...

Page 106: ...mage 1 Bound Address Register 20000000 The conÞgured value is written into the LSI1_BD register of the Universe chip PCI Slave Image 1 Translation Offset 00000000 The conÞgured value is written into the LSI1_TO register of the Universe chip PCI Slave Image 2 Control C0410000 The conÞgured value is written into the LSI2_CTL register of the Universe chip PCI Slave Image 2 Base Address Register 20000...

Page 107: ...value is written into the VSI0_CTL register of the Universe chip VMEbus Slave Image 0 Base Address Register 00000000 The conÞgured value is written into the VSI0_BS register of the Universe chip VMEbus Slave Image 0 Bound Address Register Local DRAM Size The conÞgured value is written into the VSI0_BD register of the Universe chip The value is the same as the Local Memory Found number already disp...

Page 108: ...mage 2 Bound Address Register 00000000 The conÞgured value is written into the VSI2_BD register of the Universe chip VMEbus Slave Image 2 Translation Offset 00000000 The conÞgured value is written into the VSI2_TO register of the Universe chip VMEbus Slave Image 3 Control 00000000 The conÞgured value is written into the VSI3_CTL register of the Universe chip VMEbus Slave Image 3 Base Address Regis...

Page 109: ...ured value is written into the SLSI register of the Universe chip Master Control Register 80C00000 The conÞgured value is written into the MAST_CTL register of the Universe chip Miscellaneous Control Register 52060000 The conÞgured value is written into the MISC_CTL register of the Universe chip User AM Codes 00000000 The conÞgured value is written into the USER_AM register of the Universe chip ...

Page 110: ...ENV Set Environment 6 18 6 ...

Page 111: ...on level of the document such as Ò xx2Ó the second revision of a manual a supplement bears the same number as the manual but has a suffix such as Ò xx2A1Ó the first supplement to the second revision of the manual Table A 1 Motorola Computer Group Documents Document Title Publication Number MVME2300 Series VME Processor Module Installation and Use this manual V2300A IH MVME2300 Series VME Processor...

Page 112: ...urce Publication Number PowerPC 603TM RISC Microprocessor Technical Summary Literature Distribution Center for Motorola Telephone 1 800 441 2447 FAX 602 994 6430 or 303 675 2150 E mail ldcformotorola hibbertco com MPC603 D PowerPC 603TM RISC Microprocessor UserÕs Manual Literature Distribution Center for Motorola Telephone 1 800 441 2447 FAX 602 994 6430 or 303 675 2150 E mail ldcformotorola hibbe...

Page 113: ...ustomer Support Center or nearest Sales OfÞce 2900 Semiconductor Drive P O Box 58090 Santa Clara California 95052 8090 Telephone 1 800 272 9959 PC16550DV 82378 System I O SIO PCI to ISA Bridge Controller Intel Corporation Literature Sales P O Box 7641 Mt Prospect Illinois 60056 7641 Telephone 1 800 548 4725 290473 003 DECchip 21140 PCI Fast Ethernet LAN Controller Hardware Reference Manual Digital...

Page 114: ... SGS Thomson Microelectronics Group Marketing Headquarters or nearest Sales OfÞce 1000 East Bell Road Phoenix Arizona 85022 Telephone 602 867 6100 M48T59 Universe User Manual Tundra Semiconductor coproration 603 March Road Kanata ON K2K 2M5 Canada Telephone 1 800 267 7231 OR 695 High Glen Drive San Jose California 95133 USA Telephone 408 258 3600 FAX 408 258 3659 Universe Part Number 9000000 MD303...

Page 115: ...a 85260 3415 Telephone 602 951 8866 FAX 602 951 0720 ANSI VITA 1 1994 NOTE An earlier version of this speciÞcation is available as Versatile Backplane Bus VMEbus Institute of Electrical and Electronics Engineers Inc Publication and Sales Department 345 East 47th Street New York New York 10017 21633 Telephone 1 800 678 4333 ANSI IEEE Standard 1014 1987 OR Microprocessor system bus for 1 to 4 byte d...

Page 116: ...al Component Interconnect PCI Local Bus SpeciÞcation Revision 2 0 PCI Special Interest Group P O Box 14070 Portland Oregon 97214 4070 Marketing Help Line Telephone 503 696 6111 Document SpeciÞcation Ordering Telephone 1 800 433 5177or 503 797 4207 FAX 503 234 6762 PCI Local Bus SpeciÞcation PowerPC Reference Platform PRP SpeciÞcation Third Edition Version 1 0 Volumes I and II International Busines...

Page 117: ... OR IBM 1580 Route 52 Bldg 504 Hopewell Junction NY 12533 7531 Telephone 1 800 PowerPC OR Morgan Kaufmann PUblishers Inc 340 Pine street Sixth Floor San Francisco CA 94104 3205 USA Telephone 413 392 2665 FAX 415 982 2665I Interface Between Data Terminal Equipment and Data Circuit Terminating Equipment Employing Serial Binary Data Interchange EIA 232 D Electronic Industries Association Engineering ...

Page 118: ...Ordering Related Documentation A 8 A ...

Page 119: ...imated 5 2 60ns EDO to 8 7 50ns EDO 16KB 16KB I D on chip cache MPC604 300 MHz SPECint95 10 8 50ns EDO 32KB 32KB I D on chip cache Memory DRAM 16MB 32MB 64MB or 128MB ECC protected Flash 1MB via two 32 pin PLCC sockets 4MB via surface mount TOD clock device M48T59 8KB NVRAM Timers One watchdog timer time out generates reset Four real time 16 bit programmable timers Power requirements with no PMCs ...

Page 120: ...ic double wide 149 0 mm x 149 0 mm PMC I O Front panel and or VMEbus P2 I O PCI expansion connector Address Data A32 D32 D46 114 pin connector PCI bus clock 33 MHz Signalling 5V Peripheral Computer Interface PCI PCI bridge PCIbus 32 64 bit 33MHz VMEbus ANSI VITA 1 1994 VME64 previously IEEE STD 1014 DTB master A16 A32 D08 D64 BLT DTB slave A24 A32 D08 D64 BLT UAT Arbiter Round Robin or Priority In...

Page 121: ...der test to simulate a high power density system configuration An assembly of three axial fans rated at 100 CFM per fan is placed directly under the VME card cage The incoming air temperature is measured between the fan assembly and the card cage where the incoming airstream first encounters the module under test Test software is executed as the module is subjected to ambient temperature variation...

Page 122: ...ielded cables on all external I O ports Cable shields connected to chassis ground via metal shell connectors bonded to a conductive module front panel Conductive chassis rails connected to chassis ground This provides the path for connecting shields to chassis ground Front panel screws properly tightened All peripherals were EMC compliant For minimum RF emissions it is essential that the condition...

Page 123: ...nect signals consult the support information documentation for the MVME230x contact your Motorola sales office Connector Location Table VMEbus connector P1 C 1 VMEbus connector P2 I O P2 C 2 Debug serial port RJ45 DEBUG J2 C 3 Ethernet port RJ45 10 100 BASET J3 C 4 CPU debug connector J1 C 5 PCI expansion connector J18 C 6 PMC connectors Slot 1 32 bit PCI J11 J12 C 7 64 bit PCI extension and P2 I ...

Page 124: ...0 VD11 Not Used 4 5 Not Used VD4 VBGOUT0 VD12 Not Used 5 6 GND VD5 VBGIN1 VD13 Not Used 6 7 Not Used VD6 VBGOUT1 VD14 Not Used 7 8 GND VD7 VBGIN2 VD15 Not Used 8 9 Not Used GND VBGOUT2 GND VMEGAP 9 10 GND VSYSCLK VBGIN3 VSYSFAIL VMEGA0 10 11 Not Used GND VBGOUT3 VBERR VMEGA1 11 12 GND VDS1 VBR0 VSYSRESET Not Used 12 13 Not Used VDS0 VBR1 VLWORD VMEGA2 13 14 GND VWRITE VBR2 VAM5 Not Used 14 15 Not ...

Page 125: ...VA12 Not Used 26 27 Not Used VA4 VIRQ4 VA11 Not Used 27 28 GND VA3 VIRQ3 VA10 Not Used 28 29 Not Used VA2 VIRQ2 VA9 Not Used 29 30 GND VA1 VIRQ1 VA8 Not Used 30 31 Not Used Ð12V 5VSTDBY 12V GND 31 32 GND 5V 5V 5V Not Used 32 Table C 1 P1 VMEbus Connector Pin Assignments Continued ...

Page 126: ... VA27 PMC1_13 J14 13 PMC2_10 J24 10 7 8 GND PMC1_16 J14 16 VA28 PMC1_15 J14 15 PMC2_12 J24 12 8 9 PMC2_14 J24 14 PMC1_18 J14 18 VA29 PMC1_17 J14 17 PMC2_13 J24 13 9 10 GND PMC1_20 J14 20 VA30 PMC1_19 J14 19 PMC2_15 J24 19 10 11 PMC2_17 J24 17 PMC1_22 J14 22 VA31 PMC1_21 J14 21 PMC2_16 J24 16 11 12 GND PMC1_24 J14 24 GND PMC1_23 J14 23 PMC2_18 J24 18 12 13 PMC2_20 J24 20 PMC1_26 J14 26 5V PMC1_25 J...

Page 127: ...7 PMC1_51 J14 51 PMC2_39 J24 39 26 27 PMC2_41 J24 41 PMC1_54 J14 54 VD28 PMC1_53 J14 53 PMC2_40 J24 40 27 28 GND PMC1_56 J14 56 VD29 PMC1_55 J14 55 PMC2_42 J24 42 28 29 PMC2_44 J24 44 PMC1_58 J14 58 VD30 PMC1_57 J14 57 PMC2_43 J24 43 29 30 GND PMC1_60 J14 60 VD31 PMC1_59 J14 59 PMC2_45 J24 45 30 31 PMC2_46 J24 46 PMC1_62 J14 62 GND PMC1_61 J14 61 GND 31 32 GND PMC1_64 J14 64 5V PMC1_63 J14 63 VPC ...

Page 128: ... connector are as follows Ethernet Connector 10BASET J3 The 10BaseT 100BaseTx connector is an RJ45 connector located on the front plate of the MVME230x The pin assignments for this connector are as follows Table C 3 DEBUG J2 Connector Pin Assignments 1 DCD 2 RTS 3 GND 4 TXD 5 RXD 6 GND 7 CTS 8 DTR Table C 4 10 100 BASET J3 Connector Pin Assignments 1 TD 2 TD 3 RD 4 No Connect 5 No Connect 6 RD 7 N...

Page 129: ...s The pin assignments for this connector are as follows Table C 5 Debug Connector Pin Assignments 1 PA0 GND PA1 2 3 PA2 PA3 4 5 PA4 PA5 6 7 PA6 PA7 8 9 PA8 PA9 10 11 PA10 PA11 12 13 PA12 PA13 14 15 PA14 PA15 16 17 PA16 PA17 18 19 PA18 PA19 20 21 PA20 PA21 22 23 PA22 PA23 24 25 PA24 PA25 26 27 PA26 PA27 28 29 PA28 PA29 30 31 PA30 PA31 32 33 PAPAR0 PAPAR1 34 35 PAPAR2 PAPAR3 36 37 APE RSRV 38 ...

Page 130: ...6 47 PD8 PD9 48 49 PD10 PD11 50 51 PD12 PD13 52 53 PD14 PD15 54 55 PD16 PD17 56 57 PD18 PD19 58 59 PA20 PD21 60 61 PD22 PD23 62 63 PD24 PD25 64 65 PD26 PD27 66 67 PD28 PD29 68 69 PD30 PD31 70 71 PD32 PD33 72 73 PD34 PD35 74 75 PD36 PD37 76 Table C 5 Debug Connector Pin Assignments Continued ...

Page 131: ...47 86 87 PD48 PD49 88 89 PA50 PD51 90 91 PD52 PD53 92 93 PD54 PD55 94 95 PD56 PD57 96 97 PD58 PD59 98 99 PD60 PD61 100 101 PD62 PD63 102 103 PDPAR0 PDPAR1 104 105 PDPAR2 PDPAR3 106 107 PDPAR4 PDPAR5 108 109 PDPAR6 PDPAR7 110 111 112 113 DPE DBDIS 114 Table C 5 Debug Connector Pin Assignments Continued ...

Page 132: ...3 TC0 122 123 TT4 TC1 124 125 CI TC2 126 127 WT CSE0 128 129 GLOBAL CSE1 130 131 SHARED DBWO 132 133 AACK TS 134 135 ARTY XATS 136 137 DRTY TBST 138 139 TA 140 141 TEA 142 143 DBG 144 145 DBB 146 147 ABB 148 149 TCLK_OUT CPUGNT0 150 151 CPUREQ0 152 Table C 5 Debug Connector Pin Assignments Continued ...

Page 133: ...CKSTPO 162 163 L2BG HALTED 164 165 L2CLAIM TLBISYNC 166 167 TBEN 168 169 SUSPEND 170 171 DRVMOD0 172 173 DRVMOD1 174 175 NAPRUN 176 177 SRESET1 QREQ 178 179 SRESET0 QACK 180 181 HRESET TDO 182 183 GND TDI 184 185 CPUCLK TCK 186 187 CPUCLK TMS 188 189 CPUCLK TRST 190 Table C 5 Debug Connector Pin Assignments Continued ...

Page 134: ...is connector are as follows Table C 6 J18 PCI Expansion Connector Pin Assignments 1 3 3V GND 3 3V 2 3 PCICLK PMCINTA 4 5 GND PMCINTB 6 7 PURST PMCINTC 8 9 HRESET PMCINTD 10 11 TDO TDI 12 13 TMS TCK 14 15 TRST PCIXP 16 17 PCIXGNT PCIXREQ 18 19 12V 12V 20 21 PERR SERR 22 23 LOCK SDONE 24 25 DEVSEL SBO 26 27 GND GND 28 29 TRDY IRDY 30 31 STOP FRAME 32 33 GND GND 34 35 ACK64 Reserved 36 37 REQ64 Reser...

Page 135: ...47 AD3 AD2 48 49 AD5 AD4 50 51 AD7 AD6 52 53 AD9 AD8 54 55 AD11 AD10 56 57 AD13 AD12 58 59 AD15 AD14 60 61 AD17 AD16 62 63 AD19 AD18 64 65 AD21 AD20 66 67 AD23 AD22 68 69 AD25 AD24 70 71 AD27 AD26 72 73 AD29 AD28 74 75 AD31 AD30 76 Table C 6 J18 PCI Expansion Connector Pin Assignments Continued ...

Page 136: ...AD35 AD34 86 87 AD37 AD36 88 89 AD39 AD38 90 91 AD41 AD40 92 93 AD43 AD42 94 95 AD45 AD44 96 97 AD47 AD46 98 99 AD49 AD48 100 101 AD51 AD50 102 103 AD53 AD52 104 105 AD55 AD54 106 107 AD57 AD56 108 109 AD59 AD58 110 111 AD61 AD60 112 113 AD63 AD62 114 Table C 6 J18 PCI Expansion Connector Pin Assignments Continued ...

Page 137: ...1 5V 8 7 GND Not Used 8 9 INTD Not Used 10 9 Not Used Not Used 10 11 GND Not Used 12 11 Pull up 3 3V 12 13 CLK GND 14 13 RST Pull down 14 15 GND PMCGNT1 16 15 3 3V Pull down 16 17 PMCREQ1 5V 18 17 Not Used GND 18 19 5V Vio AD31 20 19 AD30 AD29 20 21 AD28 AD27 22 21 GND AD26 22 23 AD25 GND 24 23 AD24 3 3V 24 25 GND C BE3 26 25 IDSEL1 AD23 26 27 AD22 AD21 28 27 3 3V AD20 28 29 AD19 5V 30 29 AD18 GND...

Page 138: ...C1_6 P2 A3 6 7 C BE4 GND 8 7 PMC1_7 P2 C4 PMC1_8 P2 A4 8 9 5V Vio PAR64 10 9 PMC1 _9 P2 C5 PMC1_10 P2 A5 10 11 AD63 AD62 12 11 PMC1_11 P2 C6 PMC1_12 P2 A6 12 13 AD61 GND 14 13 PMC1_13 P2 C7 PMC1_14 P2 A7 14 15 GND AD60 16 15 PMC1_15 P2 C8 PMC1_16 P2 A8 16 17 AD59 AD58 18 17 PMC1_17 P2 C9 PMC1_18 P2 A9 18 19 AD57 GND 20 19 PMC1_19 P2 C10 PMC1_20 P2 A10 20 21 5V Vio AD56 22 21 PMC1_21 P2 C11 PMC1_22...

Page 139: ...2 C23 PMC1_46 P2 A23 46 47 AD39 AD38 48 47 PMC1_47 P2 C24 PMC1_48 P2 A24 48 49 AD37 GND 50 49 PMC1_49 P2 C25 PMC1_50 P2 A25 50 51 GND AD36 52 51 PMC1_51 P2 C26 PMC1_52 P2 A26 52 53 AD35 AD34 54 53 PMC1_53 P2 C27 PMC1_54 P2 A27 54 55 AD33 GND 56 55 PMC1_55 P2 C28 PMC1_56 P2 A28 56 57 5V Vio AD32 58 57 PMC1_57 P2 C29 PMC1_58 P2 A29 58 59 Reserved Reserved 60 59 PMC1_59 P2 C30 PMC1_60 P2 A30 60 61 Re...

Page 140: ... PMCPRSNT2 5V 8 7 GND Not Used 8 9 INTD Not Used 10 9 Not Used Not Used 10 11 GND Not Used 12 11 Pull up 3 3V 12 13 CLK GND 14 13 RST Pull down 14 15 GND PMCGNT2 16 15 3 3V Pull down 16 17 PMCREQ2 5V 18 17 Not Used GND 18 19 5V Vio AD31 20 19 AD30 AD29 20 21 AD28 AD27 22 21 GND AD26 22 23 AD25 GND 24 23 AD24 3 3V 24 25 GND C BE3 26 25 IDSEL2 AD23 26 27 AD22 AD21 28 27 3 3V AD20 28 29 AD19 5V 30 29...

Page 141: ...5 6 5 PMC2_5 P2 Z3 PMC2_6 P2 D4 6 7 C BE4 GND 8 7 PMC2_7 P2 D5 PMC2_8 P2 Z5 8 9 5V Vio PAR64 10 9 PMC2_9 P2 D6 PMC2_10 P2 D7 10 11 AD63 AD62 12 11 PMC2_11 P2 Z7 PMC2_12 P2 D8 12 13 AD61 GND 14 13 PMC2_13 P2 D9 PMC2_14 P2 Z9 14 15 GND AD60 16 15 PMC2_15 P2 D10 PMC2_16 P2 D11 16 17 AD59 AD58 18 17 PMC2_17 P2 Z11 PMC2_18 P2 D12 18 19 AD57 GND 20 19 PMC2_19 P2 D13 PMC2_20 P2 Z13 20 21 5V Vio AD56 22 2...

Page 142: ... 42 43 AD41 GND 44 43 PMC2_43 P2 D29 PMC2_44 P2 Z29 44 45 GND AD40 46 45 PMC2_45 P2 D30 PMC2_46 P2 Z31 46 47 AD39 AD38 48 47 Not Used Not Used 48 49 AD37 GND 50 49 Not Used Not Used 50 51 GND AD36 52 51 Not Used Not Used 52 53 AD35 AD34 54 53 Not Used Not Used 54 55 AD33 GND 56 55 Not Used Not Used 56 57 5V Vio AD32 58 57 Not Used Not Used 58 59 Reserved Reserved 60 59 Not Used Not Used 60 61 Rese...

Page 143: ...y the simple troubleshooting steps on the following pages before calling for help or sending the board back for repair Some of the procedures will return the board to the factory debugger environment The board was tested under these conditions before it left the factory The selftests may not run in all user customized environments ...

Page 144: ...ne Try it B If the LEDs are lit the board may be in the wrong slot 1 The VME processor module should be in the Þrst leftmost slot 2 Also check that the Òsystem controllerÓ function on the board is enabled per this manual C The Òsystem consoleÓ terminal may be conÞgured incorrectly ConÞgure the system console terminal per this manual II There is a display on the terminal but input from the keyboard...

Page 145: ... as indicated If the debug prompt does not appear go to step VI B The board may need to be reset IV Debug prompt PPC1 Bug appears at powerup but the board does not autoboot A The initial debugger environment parameters may be set incorrectly 1 Start the onboard calendar clock and timer Type set mmddyyhhmm CR where the characters indicate the month day year hour and minute The date and time will be...

Page 146: ...You may need to use the cnfg command see your board Debugger Manual to change clock speed and or Ethernet Address and then later return to env CR and step 3 7 Run the selftests by typing in st CR The tests take as much as 10 minutes depending on RAM size They are complete when the prompt returns The onboard selftest is a valuable tool in isolating defects 8 The system may indicate that it has pass...

Page 147: ...uired VI The board has failed one or more of the tests listed above and cannot be corrected using the steps given A There may be some fault in the board hardware or the on board debugging and diagnostic Þrmware 1 Document the problem and return the board for service 2 Phone 1 800 222 5640 TROUBLESHOOTING PROCEDURE COMPLETE Table D 1 Troubleshooting MVME230x Modules Continued Condition Possible Pro...

Page 148: ...D 6 Troubleshooting the MVME230x D ...

Page 149: ...d twisted pair UTP of wires capable of carrying data at 10 Mbps for a maximum distance of 185 meters Also known as twisted pair Ethernet 100Base TX An Ethernet implementation in which the physical medium is an unshielded twisted pair UTP of wires capable of carrying data at 100 Mbps for a maximum distance of 100 meters Also known as fast Ethernet ACIA Asynchronous Communications Interface Adapter ...

Page 150: ...BLock Transfer A type of graphics drawing routine that moves a rectangle of data from one area of display memory to another The data specifically need not have any particular alignment BLT BLock Transfer board The term more commonly used to refer to a PCB printed circuit board Basically a flat board made of nonconducting material such as plastic or fiberglass on which chips and other electronic co...

Page 151: ...r A computer whose processor is designed to sequentially run variable length instructions many of which require several clock cycles that perform complex tasks and thereby simplify programming CODEC COder DECoder Color Difference CD The signals of R Y and B Y without the luminance Y signal The Green signals G Y can be extracted by these two signals Common Hardware Reference Platform CHRP A specifi...

Page 152: ...ed to avoid loss of data DTE Data Terminal Equipment ECC Error Correction Code ECP Extended Capability Port EEPROM Electrically Erasable Programmable Read Only Memory A memory storage device that can be written repeatedly with no special erasure fixture EEPROMs do not lose their contents when they are powered down EIDE Enhanced Integrated Drive Electronics An improved version of IDE with faster da...

Page 153: ...n non return to zero invert on 1s NRZI format at speeds up to 100 Mbps FIFO First In First Out A memory that can temporarily hold data so that the sending device can send data faster than the receiving device can accept it The sending and receiving devices typically operate asynchronously firmware The program or specific software instructions that have been more or less permanently burned into an ...

Page 154: ...hics system in which the even scanlines are refreshed in one vertical cycle field and the odd scanlines are refreshed in another vertical cycle The advantage is that the video bandwidth is roughly half that required for a non interlaced system of the same resolution This results in less costly hardware It also may make it possible to display a resolution that would otherwise be impossible on given...

Page 155: ... Interface The standard format for recording storing and playing digital music MPC Multimedia Personal Computer MPC105 The PowerPC to PCI bus bridge chip developed by Motorola for the Ultra 603 Ultra 604 system board It provides the necessary interface between the MPC603 MPC604 processor and the Boot ROM secondary cache the DRAM system memory array and the PCI bus MPC601 MotorolaÕs component desig...

Page 156: ...a more pleasing appearance nonvolatile memory A memory in which the data content is maintained whether the power supply is connected or not NTSC National Television Standards Committee USA NVRAM Non Volatile Random Access Memory OEM Original Equipment Manufacturer OMPAC Over Molded Pad Array Carrier OS Operating System The software that manages the computer resources accesses files and dispatches ...

Page 157: ...p PMC PCI Mezzanine Card POWER Performance Optimized With Enhanced RISC architecture IBM PowerPC The trademark used to describe the Performance Optimized With Enhanced RISC microprocessor architecture for Personal Computers developed by the IBM Corporation PowerPC is superscalar which means it can handle more than one instruction per clock cycle Instructions can be sent simultaneously to three typ...

Page 158: ...ystems Division which defines the devices interfaces and data formats that make up a PRP compliant system using a PowerPC processor PowerStack RISC PC System Board A PowerPC based computer board platform developed by the Motorola Computer Group It supports MicrosoftÕs Windows NT and IBMÕs AIX operating systems PRP See PowerPC Reference Platform PRP PRP compliant See PowerPC Reference Platform PRP ...

Page 159: ... a single signal Both digital and analog RGB interfaces exist RISC See Reduced Instruction Set Computer RISC ROM Read Only Memory RTC Real Time Clock SBC Single Board Computer SCSI Small Computer Systems Interface An industry standard high speed interface primarily used for secondary storage SCSI 1 provides up to 5 Mbps data transfer SCSI 2 Fast Wide An improvement over plain SCSI and includes com...

Page 160: ... programs languages operating procedures and documentation of a computer system Software is the real interface between the user and the computer SRAM Static Random Access Memory SSBLT Source Synchronous BLock Transfer standard s A set of detailed technical guidelines used as a means of establishing uniformity in an area of hardware or software development SVGA Super Video Graphics Array IBM An imp...

Page 161: ...em VGA Video Graphics Array IBM The third and most common monitor standard used today It provides up to 256 simultaneous colors and a screen resolution of 640 x 480 pixels virtual address A binary address issued by a CPU that indirectly refers to the location of information in primary memory such as main memory When data is copied from disk to main memory the physical address is changed to the vir...

Page 162: ...T The trademark representing Windows New Technology a computer operating system developed by the Microsoft Corporation XGA EXtended Graphics Array An improved IBM VGA monitor standard that provides at least 256 simultaneous colors and a screen resolution of 1024 x 768 pixels Y Signal Luminance This determines the brightness of each spot pixel on a CRT screen either color or B W systems but not the...

Page 163: ...ctive chassis rails B 4 configurable items MVME230x base board 1 8 configuration debug port 2 5 configurations MVME230x 1 2 configure PPC1Bug parameters 6 3 VMEbus interface 6 13 Configure Board Information Block CNFG 6 2 configuring the hardware 1 7 connector pin assignments C 1 console terminal 1 4 preparing 1 12 cooling requirements B 3 counters 3 19 CPU LED DS2 2 3 2 4 D debug console terminal...

Page 164: ...s timeout 1 23 H hardware configuration 1 7 diagnostics 5 10 initialization 5 3 hardware features 3 1 HE Help command 5 10 headers J15 1 10 J16 1 10 J17 1 11 help command 5 10 humidity relative B 2 I IACK and BG signals 1 22 initialization process 5 3 installation considerations 1 23 installing multiple MVME230x boards 1 24 MVME230x 1 21 MVME230x hardware 1 13 MVME230x into chassis 1 21 PCI mezzan...

Page 165: ...oot enable 6 9 Non Volatile RAM NVRAM 6 1 6 3 NVRAM BBRAM configuration area 3 12 O operating parameters 6 1 P P1 and P2 1 23 P1 and P2 connectors 1 2 C 2 parallel port 4 8 parity 1 13 2 5 PC16550 2 5 PCI bus 3 3 3 13 3 16 4 3 4 6 PCI bus latency 3 5 PCI expansion 3 13 3 15 PCI Host Bridge PHB 3 18 PCI Mezzanine Card PMC 2 6 PCI mezzanine cards slots B 2 PCI Mezzanine Cards PMCs 1 3 PCI to ECC mem...

Page 166: ...ines B 4 related documentation ordering A 1 related specifications A 5 remote control status connector 3 19 required equipment 1 1 resetting the system 2 3 4 8 restart mode 5 11 RF emissions B 4 ROMboot enable 6 8 6 12 ROMFAL 6 11 ROMNAL 6 12 S SCSI bus 6 5 SD command 5 10 secondary PMCspan installing 1 18 serial port MVME230x 2 5 set environment to bug operating system ENV 6 3 setup terminal 1 22...

Page 167: ...rse VMEbus interface ASIC 2 3 3 15 4 3 4 4 4 9 4 11 unpacking the hardware 1 7 uppercase 5 11 using the front panels 2 1 V vibration operating B 2 VME Processor Module board layout 1 9 VME Processor Module MVME230x 1 2 VMEbus 3 3 B 2 address data configurations 1 23 backplane 1 2 connectors C 2 memory maps 4 3 system controller selection header J16 1 10 Universe ASIC and 3 15 VMEbus interface 6 13...

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