Motorola MVME2301, Installation And Use Manual, Page: 54 / 167

Block Diagram
3-6
3
The following table shows the access timings for various types of
transfers initiated by a 60X system bus master to PCI:
Notes
1. Write cycles are posted by the Raven ASIC.
2. Assumes no pipeline. Pipelined cycles would
improve these numbers.
3. T
arb
is assumed to be 4 system clocks (2 PCI clocks).
4.
T
ac
is assumed to be 6 system clocks (3 PCI clocks):
Medium DEVSEL# target, zero wait PCI timing.
The following table shows the ECC memory access latency for PCI-
initiated cycles.
Table 3-3. PowerPC 60x Bus to PCI Access Timing
Access Type
System Clock Periods Required For:
Total
Clocks
1st Beat 2nd Beat 3rd Beat 4th Beat
4-Beat Read (64-bit PCI
Target) 27 1 1 1 30
4-Beat Read (32-bit PCI
Target) 35 1 1 1 38
4-Beat Write (64-bit PCI
Target) 4 1 1 1 7
4-Beat Write (32-bit PCI
Target) 4 1 1 1 7
1-Beat Read (aligned, 4 bytes
or less) 20 - - - 20
1-Beat Write 4 - - - 4