Motorola M68EVB912B32, User Manual

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HARDWARE REFERENCE
68EVB912B32UM/D 4-5
4.4 TERMINAL INTERFACE
An RS-232C transceiver (U1A or U1B) links the MCU’s Serial Communications Interface to the
RS-232C DB-9 receptacle, P1. The communications parameters for this port are described in 2.5
Terminal Communications Setup.
4.5 MICROCONTROLLER
The MC68HC912B32 is the first of a family of next generation M68HC11 microcontrollers with
both on-chip memory and peripheral functions. The CPU12 is a high-speed, 16-bit processing
unit. The programming model and stack frame are identical to those of the standard M68HC11
CPU. The CPU12 instruction set is a proper superset of the M68HC11 instruction set. All
M68HC11 instruction mnemonics are accepted by CPU12 assemblers with no changes.
The EVB-resident MC68HC912B32 (U2) has seven modes of operation. These modes are
determined at reset by the state of three mode pins — BKGD, MODB, and MODA — as shown
in Table 4-2.
The EVB is factory-configured for MCU operation in the Normal Single Chip mode. In this
mode of operation, all port pins are available to the user. On-chip Flash EEPROM is used for
program execution, with byte-erasable EEPROM and some RAM available for user code/data.
Although other MCU modes are available, the EVB was designed for the Single Chip mode of
operation. There is no provision for external memory.
For more information on the CPU, refer to the CPU12 Reference Manual.
Table 4-2. CPU Mode Selection
BKGD
Through BDM IN
MODB
Header W5
MODA
Header W6
Mode Description
0 0 0 Special Single Chip
0 0 1 Special Expanded Narrow
0 1 0 Special Peripheral
0 1 1 Special Expanded Wide
1 0 0 Normal Single Chip
1 0 1 Normal Expanded Narrow
1 1 0 Reserved (currently defaults to
peripheral mode)
1 1 1 Normal Expanded Wide