Motorola M68EVB912B32, User Manual

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OPERATION
68EVB912B32UM/D 3-53
Table 3-4. Condition Code Register Bits (continued)
CCR Bit Name Description Legal Values
V Two’s Complement Overflow Flag 0 or 1
C Carry Flag 0 or 1
IM IRQ Interrupt Mask 0 or 1
XM XIRQ Interrupt Mask 0 or 1
This set of "commands" uses a CPU12 register name as the command name to allow changing
the register’s contents. Each register name or CCR bit name is entered on the command line
followed by a space, then followed by the new register or bit contents. After successful alteration
of a CPU register or CCR bit, the entire CPU register set is displayed.
restrictions:
None.
example:
>PC 700e
PC SP X Y D=A:B CCR=SXHI NZVC
700E 0A00 7315 7D62 47:44 1001 0000
>X 1000
PC SP X Y D=A:B CCR=SXHI NZVC
700E 0A00 1000 7D62 47:44 1001 0000
>C 1
PC SP X Y D=A:B CCR=SXHI NZVC
700E
0A00 1000 7D62 47:44 1001 0001
>Z 1
PC SP X Y D=A:B CCR=SXHI NZVC
700E 0A00 1000 7D62 47:44 1001 0101
>D adf7
PC SP X Y D=A:B CCR=SXHI NZVC
700E 0A00 1000 7D62 AD:F7 1001 0101
>