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DSP56000/DSP56001 USER’S MANUAL
MOTOROLA
Assembler Syntax:
LSL
D (parallel move)
Description: Logically shift bits 47–24 of the destination operand D one bit to the left
and store the result in the destination accumulator. Prior to instruction execution, bit 47
of D is shifted into the carry bit C, and a zero is shifted into bit 24 of the destination accu-
mulator D. This instruction is a 24-bit operation. The remaining bits of the destination
operand D are not affected. If a zero shift count is specified, the carry bit is cleared. The
difference between LSL and ASL is that LSL operates on only A1 or B1 and always
clears the V bit.
Example:
:
LSL B #$7F,R0
;shift B1 one bit to the left, set up R0
:
Explanation of Example: Prior to execution, the 56-bit B accumulator contains the
value $00:F01234:13579B. The execution of the LSL B instruction shifts the 24-bit value
in the B1 register one bit to the left and stores the result back in the B1 register.
Condition Codes:
L — Set if data limiting has occurred during parallel move
N — Set if bit 47 of A or B result is set
Z— Set if bits 47–24 of A or B result are zero
V — Always cleared
C — Set if bit 47 of A or B was set prior to instruction execution
LSL
Logical Shift Left
LSL
47
24
C
0 (parallel move)
Operation:
Before Execution
After Execution
B
B
$00:F01234:13579B
SR
SR
$0300
$0309
$00:E02468:13579B
MR
CCR
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0
LF
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T
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S1
S0
I1
I0
**
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V
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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