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DSP56000/DSP56001 USER’S MANUAL

MOTOROLA

Operation:

If

D[55]

⊕

S[23]=1,

Assembler Syntax:

DIV

S,D

Description:
Divide the destination operand D by the source operand S and store the result in the
destination accumulator D. The 48-bit dividend must be a positive fraction which has
been sign extended to 56-bits and is stored in the full 56-bit destination accumula-
tor D. The 24-bit divisor is a signed fraction and is stored in the source operand S.
Each DIV iteration calculates one quotient bit using a nonrestoring fractional division
algorithm (see description on the next page). After the execution of the first DIV instruc-
tion, the destination operand holds both the partial remainder and the formed quotient.
The partial remainder occupies the high-order portion of the destination accumulator D
and is a signed fraction. The formed quotient occupies the low-order portion of the desti-
nation accumulator D (A0 or B0) and is a positive fraction. One bit of the formed quotient
is shifted into the LS bit of the destination accumulator at the start of each DIV iteration.
The formed quotient is the true quotient if the true quotient is positive. If the true quotient
is negative, the formed quotient must be negated. Valid results are obtained only
when |D| < |S| and the operands are interpreted as fractions. Note that this condition
ensures that the magnitude of the quotient is less than one (i.e., is fractional) and pre-
cludes division by zero.

The DIV instruction calculates one quotient bit based on the divisor and the previous par-
tial remainder. To produce an N-bit quotient, the DIV instruction is executed N times
where N is the number of bits of precision desired in the quotient, 1;leN;le24. Thus, for a
full-precision (24 bit) quotient, 24 DIV iterations are required. In general, executing the
DIV instruction N times produces an N-bit quotient and a 48-bit remainder which has
(48–N) bits of precision and whose N MS bits are zeros. The partial remainder is not a
true remainder and must be corrected due to the nonrestoring nature of the division algo-

DIV

Divide Interation

DIV

55

47

23

0

C+S

then

55

47

23

0

C–S

else

Destination Accumulator D

Destination Accumulator D

where

⊕

denotes the logical exclusive OR operator

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Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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Summary of Contents for Freescale Semiconductor DSP56000

Page 1: ...tional it will be shown in parenthesis in the assembler syntax field 3 Description A complete text description of the instruction is given together with any special cases and or condition code anomalies of which the user should be aware when using that instruction 4 Example An example of the use of the instruction is given The example is shown in DSP56000 DSP56001 assembler source code format Most...

Page 2: ... Depending on the context registers refer to either the register itself or the contents of the register A 3 ADDRESSING MODES The addressing modes are grouped into three categories register direct address regis ter indirect and special These addressing modes are summarized in Table A 2 All address calculations are performed in the address ALU to minimize execution time and loop overhead Addressing ...

Page 3: ...gister X1 or X0 24 Bits Yn Input Register Y1 or Y0 24 Bits An Accumulator Registers A2 A1 A0 A2 8 Bits A1 and A0 24 Bits Bn Accumulator Registers B2 B1 B0 B2 8 Bits B1 and B0 24 Bits X Input Register X X1 X0 48 Bits Y Input Register Y Y1 Y0 48 Bits A Accumulator A A2 A1 A0 56 Bits B Accumulator B B2 B1 B0 56 BIts AB Accumulators A and B A1 B1 48 Bits BA Accumulators B and A B1 A1 48 Bits A10 Accum...

Page 4: ...nes Extended Specifiies the Contents of the Specified Address X X Memory Reference Y Y Memory Reference L Long Memory Reference X Y P Program Memory Reference Address Operands PC Program Counter Register 16 Bits MR Mode Register 8 Bits CCR Condition Code Register 8 Bits SR Status Register MR CCR 16 Bits OMR Operating Mode Register 8 Bits LA Hardware Loop Address Register 16 Bits LC Hardware Loop C...

Page 5: ...ue onto the System Stack SS Operator PULL Pull Specified Value from the System Stack SS Operator READ Read the Top of the System Stack SS Operator PURGE Delete the Top Value on the System Stack SS Operator Absolute Value Operator Unary Operators Addition Operator Subtraction Operator Multiplication Operator Division Operator Logical Inclusive OR Operator Logical AND Operator Logical Exclusive OR O...

Page 6: ...Flag Bit Indicating When a DO Loop is in Progress T Trace Mode Bit Indicating if the Tracing Function has been Enabled S1 S0 Scaling Mode Bits Indicating the Current Scaling Mode I1 I0 Interrupt Mask Bits Indicating the Current Interrupt Priority Level Mode Register MR Symbols L Limit Bit Indicating Arithmetic Overflow and or Data Shifting Limiting E Extension Bit Indicating if the Integer Portion...

Page 7: ...or RTS Instruction wio Number of Wait States Used in Accessing External I O wp Number of Wait States Used in Accessing External P Memory wx Number of Wait States Used in Accessing External X Memory wy Number of Wait States Used in Accessing External Y Memory Instruction Timing Symbols Optional Letter Operand or Operation Any Arithmetic or Logical Instruction Which Allows Parallel Moves EXT Extensi...

Page 8: ...Postincrement by Offset Nn Yes X X X X X Postdecrement by Offset Nn Yes X X X X Indexed by Offset Nn Yes X X X X Predecrement by 1 Yes X X X X Special Immediate Data No X Absolute Address No X X X X Immediate Short Data No X Short Jump Address No X Absolute Short Address No X X X X I O Short Address No X X Implicit No X X X NOTE S System Stack Reference X X Memory Reference C Program Controller Re...

Page 9: ... 110 100 X xxxxxx Absolute Address 110 000 X X xxxx Immediate Short Data xx Short Jump Address X xxx Absolute Short Address X aa I O Short Address X pp Implicit X Update Mode U The update addressing mode is used to modify address registers without any associated data move Parallel Mode P The parallel addressing mode is used in instructions where two effective addresses are required Memory Mode M T...

Page 10: ... ALU calculations or by data transfers over the X Y or global data buses The L bit is a latching overflow bit which indicates that an overflow has occurred in the data ALU or that data limiting has occurred when moving the contents of the Aand or lz B accumulators The standard definition of the condition code bits is as follows Exceptions to these standard definitions are given in Table A 5 16 Bit...

Page 11: ...s that the result cannot be represented in the 56 bit accumulator thus the accumulator has overflowed Cleared other wise C Carry Bit Set if a carry is generated out of the MS bit of the A or B result of an addition or if a borrow is generated out of the MS bit of the A or B result of a subtraction The carry or borrow is generated out of bit 55 of the A or B result Cleared otherwise Table A 5 detai...

Page 12: ...otherwise 12 Set according to the value pulled from the stack 13 If the status register SR is specified as a destination operand set according to the corresponding bit of the source operand If SR is not specified as a destination operand the L bit is set if data limiting occurred All bits are not affected otherwise 14 Set if limiting occurs not affected otherwise Mnemonic L E U N Z V C Notes Mnemo...

Page 13: ...TE The signed integer portion of an accumulator is NOT necessarily the same as either the A2 or B2 extension register portion of that accumulator The signed integer portion of an accumulator is defined according to the scaling mode be ing used and can consist of the MS 8 9 or 10 bits of an accumulator Refer to A 4 CONDITION CODE COMPUTATION for complete details Freescale Semiconductor I Freescale ...

Page 14: ...using the standard 56 bit fixed point twos complement data representation Data limiting does not occur i e A is not set to the limiting value of 7F FFFFFF FFFFFF Condition Codes L Set if limiting parallel move or overflow has occurred in result E Set if the signed integer portion of A or B result is in use U Set if A or B result is unnormalized N Set if bit 55 of A or B result is set Z Set if A or...

Page 15: ... d A 0 B 1 Timing 2 mv oscillator clock cycles Memory 1 mv program words 23 8 7 4 3 0 DATA BUS MOVE FIELD 0 0 1 0 d 1 1 0 OPTIONAL EFFECTIVE ADDRESS EXTENSION ABS Absolute Value ABS Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 16: ... 96 bit addition using the ADC instruction Prior to execution of the ADD and ADC instructions the double precision 96 bit value 000000 000001 800000 000000 is loaded into the Y and X registers Y X respectively The other double precision 96 bit value 000000 000001 800000 000000 is loaded into the B and A accumulators B A respec tively Since the 48 bit value loaded into the A accumulator is automati...

Page 17: ...ult Note The definition of the E and U bits varies according to the scaling mode being used Refer to A 4 CONDITION CODE COMPUTATION for complete details Instruction Format ADC S D Opcode Instruction Fields S D J d X A 0 0 X B 0 1 Y A 1 0 Y B 1 1 Timing 2 mv oscillator clock cycles Memory 1 mv program words MR CCR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LF T S1 S0 I1 I0 L E U N Z V C 23 8 7 4 3 0 DAT...

Page 18: ... execution the 24 bit X0 register contains the value FFFFFF and the 56 bit A accumulator contains the value 00 000100 000000 The ADD instruction automatically appends the 24 bit value in the X0 register with 24 LS zeros sign extends the resulting 48 bit long word to 56 bits and adds the result to the 56 bit A accumulator Thus 24 bit operands are added to the MSP portion of A or B A1 or B1 because ...

Page 19: ...es according to the scaling mode being used Refer to A 4 CONDITION CODE COMPUTATION for complete details Instruction Format ADD S D Opcode Instruction Fields S D J J J d S D J J J d S D J J J d B A 0 0 1 0 X0 A 1 0 0 0 Y1 A 1 1 1 0 A B 0 0 1 1 X0 B 1 0 0 1 Y1 B 1 1 1 1 X A 0 1 0 0 Y0 A 1 0 1 0 X B 0 1 0 1 Y0 B 1 0 1 1 Y A 0 1 1 0 X1 A 1 1 0 0 Y B 0 1 1 1 X1 B 1 1 0 1 Timing 2 mv oscillator clock c...

Page 20: ...23 and the 56 bit B accumulator contains the value 00 005000 000000 The ADDL A B instruction adds two times the value in the B accu mulator to the value in the A accumulator and stores the 56 bit result in the B accumula tor Condition Codes L Set if limiting parallel move or overflow has occurred in result E Set if the signed integer portion of A or B result is in use U Set if A or B result is unn...

Page 21: ... details Instruction Format ADDL S D Opcode Instruction Fields S D d B A 0 A B 1 Timing 2 mv oscillator clock cycles Memory 1 mv program words 23 8 7 4 3 0 DATA BUS MOVE FIELD 0 0 0 1 d 0 1 0 OPTIONAL EFFECTIVE ADDRESS EXTENSION ADDL Shift Left and Add Accumulators ADDL Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 22: ...t A accumulator contains the value 80 000000 2468AC and the 56 bit B accumulator contains the value 00 013570 000000 The ADDR B A instruction adds one half the value in the A accu mulator to the value in the B accumulator and stores the 56 bit result in the A accumula tor Condition Codes L Set if limiting parallel move or overflow has occurred in result E Set if the signed integer portion of A or ...

Page 23: ...details Instruction Format ADDR S D Opcode Instruction Fields S D d B A 0 A B 1 Timing 2 mv oscillator clock cycles Memory 1 mv program words 23 8 7 4 3 0 DATA BUS MOVE FIELD 0 0 0 0 d 0 1 0 OPTIONAL EFFECTIVE ADDRESS EXTENSION ADDR Shift Right and Add Accumulators ADDR Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 24: ...F0000 and the 56 bit A accumulator contains the value 00 123456 789ABC The AND X0 A instruction logically ANDs the 24 bit value in the X0 register with bits 47 24 of the A accumulator A1 and stores the result in the A accumulator with bits 55 48 and 23 0 unchanged Condition Codes L Set if data limiting has occurred during parallel move N Set if bit 47 of A or B result is set Z Set if bits 47 24 of...

Page 25: ... 1 only B1 is changed Y 0 0 1 Y 1 1 1 Timing 2 mv oscillator clock cycles Memory 1 mv program words 23 8 7 4 3 0 DATA BUS MOVE FIELD 0 1 J J d 1 1 0 OPTIONAL EFFECTIVE ADDRESS EXTENSION AND Logical AND AND Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 26: ...r carry bit C in cond code register Explanation of Example Prior to execution the 8 bit condition code register CCR contains the value 31 The AND FE CCR instruction logically ANDs the immediate 8 bit value FE with the contents of the condition code register and stores the result in the condition code register Condition Codes For CCR Operand L Cleared if bit 6 of the immediate operand is cleared E ...

Page 27: ...ese oper ands Instruction Format AND I xx D Opcode Instruction Fields xx 8 bit Immediate Short Data i i i i i i i i D E E MR 0 0 CCR 0 1 OMR 1 0 Timing 2 oscillator clock cycles Memory 1 program word 23 16 15 8 7 0 0 0 0 0 0 0 0 0 i i i i i i i i 1 0 1 1 1 0 E E ANDI AND Immediate with Control Register ANDI Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product ...

Page 28: ...2345 012345 The execution of the ASL A instruction shifts the 56 bit value in the A accumulator one bit to the left and stores the result back in the A accumulator Condition Codes L Set if limiting parallel move or overflow has occurred in result E Set if the signed integer portion of A or B result is in use U Set if A or B result is unnormalized N Set if bit 55 of A or B result is set Z Set if A ...

Page 29: ...lete details Instruction Format ASL D Opcode Instruction Fields D d A 0 B 1 Timing 2 mv oscillator clock cycles Memory 1 mv program words 23 8 7 4 3 0 DATA BUS MOVE FIELD 0 0 1 1 d 0 1 0 OPTIONAL EFFECTIVE ADDRESS EXTENSION ASL Arithmetic Shift Accumulator Left ASL Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 30: ...back in the B accu mulator Condition Codes L Set if limiting parallel move or overflow has occurred in result E Set if the signed integer portion of A or B result is in use U Set if A or B result is unnormalized N Set if bit 55 of A or B result is set Z Set if A or B result equals zero V Always cleared C Set if bit 0 of A or B was set prior to instruction execution Note The definition of the E and...

Page 31: ... Instruction Fields D d A 0 B 1 Timing 2 mv oscillator clock cycles Memory 1 mv program words 23 8 7 4 3 0 DATA BUS MOVE FIELD 0 0 1 0 d 0 1 0 OPTIONAL EFFECTIVE ADDRESS EXTENSION ASR Arithmetic Shift Accumulator Right ASR Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 32: ...ion is comple mented The bit to be tested is selected by an immediate bit number from 0 23 This instruction performs a read modify write operation on the destination location using two destination accesses before releasing the bus This instruction provides a test and change capability which is useful for synchronizing multiple processors using a shared memory This instruction can use all memory al...

Page 33: ... E Changed if bit 5 is specified Not affected otherwise L Changed if bit 6 is specified Not affected otherwise For other destination operands C Set if bit tested is set Cleared otherwise V Not affected Z Not affected N Not affected U Not affected E Not affected L Not affected MR Status Bits For destination operand SR I0 Changed if bit 8 is specified Not affected otherwise I1 Changed if bit 9 is sp...

Page 34: ...it Number bbbbb Rn Nn 0 0 0 r r r X Memory 0 00000 Rn Nn 0 0 1 r r r Y Memory 1 Rn 0 1 0 r r r Rn 0 1 1 r r r Rn 1 0 0 r r r 10111 Rn Nn 1 0 1 r r r Rn 1 1 1 r r r Absolute address 1 1 0 0 0 0 where rrr refers to an address register R0 R7 Timing 4 mvb oscillator clock cycles Memory 1 ea program words 23 16 15 8 7 0 OPTIONAL EFFECTIVE ADDRESS EXTENSION 0 0 0 0 1 0 1 1 0 1 M M M R R R 0 S 0 b b b b ...

Page 35: ...ords Instruction Format BCHG n X pp BCHG n Y pp Opcode Instruction Fields n bit number bbbbb ea 6 bit I O Short Address pppppp I O Short Address pppppp Memory SpaceS Bit Number bbbbb 000000 X Memory 0 00000 Y Memory 1 10111 111111 Timing 4 mvb oscillator clock cycles BCHG Bit Test and Change BCHG 23 16 15 8 7 0 0 0 0 0 1 0 1 1 0 0 a a a a a a 0 S 0 b b b b b 23 16 15 8 7 0 0 0 0 0 1 0 1 1 1 0 p p ...

Page 36: ...0 0 1 D D D 8 address registers in AGU 0 1 0 T T T 10111 8 address offset registers in AGU 0 1 1 N N N 8 address modifier registers in AGU 1 0 0 F F F 8 program controller registers 1 0 1 G G G See A 9 INSTRUCTION ENCODING and Table A 18 for specific register encodings Timing 4 mvb oscillator clock cycles Memory 1 ea program words 23 16 15 8 7 0 0 0 0 0 1 0 1 1 1 1 D D D D D D 0 1 0 b b b b b BCHG...

Page 37: ...leared The bit to be tested is selected by an immediate bit number from 0 23 This instruction performs a read modify write operation on the destination location using two destination accesses before releasing the bus This instruction provides a test and clear capability which is useful for synchronizing multiple processors using a shared memory This instruction can use all memory alterable address...

Page 38: ...nged if bit 5 is specified Not affected otherwise L Changed if bit 6 is specified Not affected otherwise For other destination operands C Set if bit tested is set Cleared otherwise V Not affected Z Not affected N Not affected U Not affected E Not affected L Not affected MR Status Bits For destination operand SR I0 Changed if bit 8 is specified Not affected otherwise I1 Changed if bit 9 is specifie...

Page 39: ...it Number bbbbb Rn Nn 0 0 0 r r r X Memory 0 00000 Rn Nn 0 0 1 r r r Y Memory 1 Rn 0 1 0 r r r Rn 0 1 1 r r r Rn 1 0 0 r r r 10111 Rn Nn 1 0 1 r r r Rn 1 1 1 r r r Absolute address 1 1 0 0 0 0 where rrr refers to an address register R0 R7 Timing 4 mvb oscillator clock cycles Memory 1 ea program words 23 16 15 8 7 0 OPTIONAL EFFECTIVE ADDRESS EXTENSION 0 0 0 0 1 0 1 0 0 1 M M M R R R 0 S 0 b b b b ...

Page 40: ...tion Format BCLR n X pp BCLR n Y pp Opcode Instruction Fields n bit number bbbbb ea 6 bit I O Short Address pppppp I O Short Address pppppp Memory SpaceS Bit Number bbbbb 000000 X Memory 0 00000 Y Memory 1 10111 111111 Timing 4 mvb oscillator clock cycles Memory 1 ea program words BCLR Bit Test and Clear BCLR 23 16 15 8 7 0 0 0 0 0 1 0 1 0 0 0 a a a a a a 0 S 0 b b b b b 23 16 15 8 7 0 0 0 0 0 1 0...

Page 41: ... address registers in AGU 0 1 0 T T T 10111 8 address offset registers in AGU 0 1 1 N N N 8 address modifier registers in AGU 1 0 0 F F F 8 program controller registers 1 0 1 G G G See A 9 INSTRUCTION ENCODING and Table A 18 for specific register encodings Timing 4 mvb oscillator clock cycles Memory 1 ea program words 23 16 15 8 7 0 0 0 0 0 1 0 1 0 1 1 D D D D D D 0 1 0 b b b b b BCLR Bit Test and...

Page 42: ...set The bit to be tested is selected by an immediate bit number from 0 23 This instruction performs a read modify write operation on the destination location using two destination accesses before releasing the bus This instruction provides a test and set capability which is use ful for synchronizing multiple processors using a shared memory This instruction can use all memory alterable addressing ...

Page 43: ...ed if bit 5 is specified Not affected otherwise L Changed if bit 6 is specified Not affected otherwise For other destination operands C Set if bit tested is set Cleared otherwise V Not affected Z Not affected N Not affected U Not affected E Not affected L Not affected MR Status Bits For destination operand SR I0 Changed if bit 8 is specified Not affected otherwise I1 Changed if bit 9 is specified ...

Page 44: ...it Number bbbbb Rn Nn 0 0 0 r r r X Memory 0 00000 Rn Nn 0 0 1 r r r Y Memory 1 Rn 0 1 0 r r r Rn 0 1 1 r r r Rn 1 0 0 r r r 10111 Rn Nn 1 0 1 r r r Rn 1 1 1 r r r Absolute address 1 1 0 0 0 0 where rrr refers to an address register R0 R7 Timing 4 mvb oscillator clock cycles Memory 1 ea program words 23 16 15 8 7 0 OPTIONAL EFFECTIVE ADDRESS EXTENSION 0 0 0 0 1 0 1 0 0 1 M M M R R R 0 S 1 b b b b ...

Page 45: ...ion Format BSET n X pp BSET n Y pp Opcode Instruction Fields n bit number bbbbb ea 6 bit I O Short Address pppppp I O Short Address pppppp Memory SpaceS Bit Number bbbbb 000000 X Memory 0 00000 Y Memory 1 10111 111111 Timing 4 mvb oscillator clock cycles Memory 1 ea program words BSET Bit Test and Clear BSET 23 16 15 8 7 0 0 0 0 0 1 0 1 0 01 0 a a a a a a 0 S 1 b b b b b 23 16 15 8 7 0 0 0 0 0 1 0...

Page 46: ...8 address registers in AGU 0 1 0 T T T 10111 8 address offset registers in AGU 0 1 1 N N N 8 address modifier registers in AGU 1 0 0 F F F 8 program controller registers 1 0 1 G G G See A 9 INSTRUCTION ENCODING and Table A 18 for specific register encodings Timing 4 mvb oscillator clock cycles Memory 1 ea program words 23 16 15 8 7 0 0 0 0 0 1 0 1 0 1 1 D D D D D D 0 1 1 b b b b b BSET Bit Test an...

Page 47: ... use all memory alterable addressing modes Example BTST 0 X FFEE read SSI serial input flag IF1 into C bit ROL A rotate carry bit C into LSB of A1 Explanation of Example Prior to execution the 24 bit X location X FFEE I O SSI sta tus register contains the value 000002 The execution of the BTST 1 X FFEE instruction tests the state of the 1st bit serial input flag IF1 in X FFEE and sets the carry bi...

Page 48: ...k Pointer For destination operand SSH SP Decrement by 1 For other destination operands Instruction Format BTST n X ea BTST n Y ea Opcode MR CCR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LF T S1 S0 I1 I0 L E U N Z V C BTST Bit Test and Set BTST 23 16 15 8 7 0 OPTIONAL EFFECTIVE ADDRESS EXTENSION 0 0 0 0 1 0 1 1 0 1 M M M R R R 0 S 1 b b b b b Freescale Semiconductor I Freescale Semiconductor Inc For Mo...

Page 49: ...n address register R0 R7 Timing 4 mvb oscillator clock cycles Memory 1 ea program words Instruction Format BTST n X aa BTST n Y aa Opcode Instruction Fields n bit number bbbbb aa 6 bit Absolute Short Address aaaaaa Absolute Short Address aaaaaa Memory SpaceS Bit Number bbbbb 000000 X Memory 0 00000 Y Memory 1 10111 111111 Timing 4 mvb oscillator clock cycles Memory 1 ea program words BTST Bit Test...

Page 50: ...iming 4 mvb oscillator clock cycles Memory 1 ea program words Instruction Format BTST n D Opcode Instruction Fields n bit number bbbbb D destination register DDDDDD xxxx 16 bit Absolute Address in extension word 23 16 15 8 7 0 0 0 0 0 1 0 1 1 1 0 p p p p p p 0 S 1 b b b b b BTST Bit Test BTST 23 16 15 8 7 0 0 0 0 0 1 0 1 1 1 1 D D D D D D 0 1 1 b b b b b Freescale Semiconductor I Freescale Semicon...

Page 51: ...10111 8 address offset registers in AGU 0 1 1 N N N 8 address modifier registers in AGU 1 0 0 F F F 8 program controller registers 1 0 1 G G G See A 9 INSTRUCTION ENCODING and Table A 18 for specific register encodings Timing 4 mvb oscillator clock cycles Memory 1 ea program words BTST Bit Test BTST Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to ww...

Page 52: ...5678 9ABCDE The execution of the CLR A instruction clears the 56 bit A accumulator to zero Condition Codes L Set if data limiting has occurred during parallelmove E Always cleared U Always set N Always cleared Z Always set V Always cleared CLR Clear Accumulator CLR Before Execution After Execution A A 12 345678 9ABCDE 00 000000 000000 MR CCR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LF T S1 S0 I1 I0 L...

Page 53: ...d A 0 B 1 Timing 2 mv oscillator clock cycles Memory 1 mv program words 23 8 7 4 3 0 DATA BUS MOVE FIELD 0 0 0 1 d 0 1 1 OPTIONAL EFFECTIVE ADDRESS EXTENSION CLR Clear Accumulator CLR Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 54: ...ot represent the correct sign extension This note par ticularly applies to the case where it is extended to compare 24 bit operands such as X0 with A1 Example CMP Y0 B X0 X R6 N6 Y1 Y R0 comp Y0 and B save X0 Y1 Explanation of Example Prior to execution the 56 bit B accumulator contains the value 00 000020 000000 and the 24 bit Y0 register contains the value 000024 The execution of the CMP Y0 B in...

Page 55: ...cording to the scaling mode being used Refer to A 4 CONDITION CODE COMPUTATION for complete details Instruction Format CMP S1 S2 Opcode Instruction Fields S1 S2 J J J d S1 S2 J J J d B A 0 0 0 0 Y0 B 1 0 1 1 A B 0 0 0 1 X1 A 1 1 0 0 X0 A 1 0 0 0 X1 B 1 1 0 1 X0 B 1 0 0 1 Y1 A 1 1 1 0 Y0 A 1 0 1 0 Y1 B 1 1 1 1 Timing 2 mv oscillator clock cycles Memory 1 mv program words MR CCR 15 14 13 12 11 10 9 ...

Page 56: ...ect sign extension This note par ticularly applies to the case where it is extended to compare 24 bit operands such as X0 with A1 Example CMPM X1 A BA L R4 comp Y0 and B save X0 Y1 Explanation of Example Prior to execution the 56 bit A accumulator contains the value 00 000006 000000 and the 24 bit X1 register contains the value FFFFF7 The execution of the CMPM X1 A instruction automatically append...

Page 57: ... scaling mode being used Refer to A 4 CONDITION CODE COMPUTATION for complete details Instruction Format CMPM S1 S2 Opcode Instruction Fields S1 S2 J J J d S1 S2 J J J d S1 S2 J J J d B A 0 0 0 0 X0 B 1 0 0 1 X1 A 1 1 0 0 A B 0 0 0 1 Y0 A 1 0 1 0 X1 B 1 1 0 1 X0 A 1 0 0 0 Y0 B 1 0 1 1 Y1 A 1 1 1 0 Y1 B 1 1 1 1 Timing 2 mv oscillator clock cycles Memory 1 mv program words MR CCR 15 14 13 12 11 10 9...

Page 58: ...on The formed quotient is the true quotient if the true quotient is positive If the true quotient is negative the formed quotient must be negated Valid results are obtained only when D S and the operands are interpreted as fractions Note that this condition ensures that the magnitude of the quotient is less than one i e is fractional and pre cludes division by zero The DIV instruction calculates o...

Page 59: ...ibed was a 1 i e the sign bits were different the source operand S is added to the accumulator If the result of the exclusive OR operation was a 0 i e the sign bits were the same the source operand S is subtracted from the accumulator Due to the automatic sign extension of the 24 bit signed divisor the addition or subtraction opera tion correctly sets the carry bit C of the condition code register...

Page 60: ...s that the sign extended 56 bit signed fractional dividend is stored in the A accumulator and that the 24 bit signed fractional divisor is stored in the X0 register This routine produces a full 24 bit signed quotient and a 48 bit signed remainder This routine may be greatly simplified for the case in which only positive fractional oper ands are used to produce a 24 bit positive quotient and a 48 b...

Page 61: ...on note enti tled Fractional and Interger Arithmetic Using the DSP56001 For extended precision division i e for N bit quotients where N 24 the DIV instruction is no longer applicable and a user defined N bit division routine is required For further information on division algorithms refer to pages 524 530 of Theory and Application of Digital Signal Processing by Rabiner and Gold Prentice Hall 1975...

Page 62: ...A 1 0 0 X0 B 0 0 1 X1 B 1 0 1 Y0 A 0 1 0 Y1 A 1 1 0 Y0 B 0 1 1 Y1 B 1 1 1 Timing 2 oscillator clock cycles Memory 1 program word 23 16 15 8 7 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 J J d 0 0 0 DIV Divide Iteration DIV Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 63: ...inated by the destination operand previously shown as expr No overhead other than the exe cution of this DO instruction is required to set up this loop DO loops can be nested and the loop count can be passed as a parameter During the first instruction cycle the current contents of the loop address LA and the loop counter LC registers are pushed onto the system stack The DO instruction s source ope...

Page 64: ... processing begins When executing a DO loop the instructions are actually fetched each time through the loop Therefore a DO loop can be interrupted DO loops can also be nested When DO loops are nested the end of loop addresses must also be nested and are not allowed to be equal The assembler generates an error message when DO loops are improperly nested Nested DO loops are illustrated in the examp...

Page 65: ...on itself and LA cannot be used as a target for jumps to subroutine i e JSR JScc JSSET or JSCLR to LA A DO instruction cannot be repeated using the REP instruction The following instructions cannot begin at the indicated position s near the end of a DO loop At LA 2 LA 1 and LA DO MOVEC from SSH MOVEM from SSH MOVEP from SSH MOVEC to LA LC SR SP SSH or SSL MOVEM to LA LC SR SP SSH or SSL MOVEP to L...

Page 66: ...instruction in a DO loop changes an address register and the first instruction at the top of the DO loop uses that same address register The top instruction becomes the following instruction because of the loop construct Similarly since the DO instruction accesses the program controller registers the DO instruction must not be immediately preceded by any of the following instructions Immediately b...

Page 67: ...ruction Fields ea 6 bit Effective Address MMMRRR expr 16 bit Absolute Address in 24 bit extension word Effective Addressing Mode M M M R R R Memory SpaceS Rn Nn 0 0 0 r r r X Memory 0 Rn Nn 0 0 1 r r r Y Memory 1 Rn 0 1 0 r r r Rn 0 1 1 r r r Rn 1 0 0 r r r Rn Nn 1 0 1 r r r Rn 1 1 1 r r r where rrr refers to an address register R0 R7 Timing 6 mv oscillator clock cycles Memory 2 program words MR C...

Page 68: ...xxx expr Opcode Instruction Fields xxx 12 bit Immediate Short Data hhhhiiiiiiii expr 16 bit Absolute Address in 24 bit extension word Immediate Short Data hhhh i i i i i i i i 000000000000 111111111111 Timing 6 mv oscillator clock cycles DO Start Hardware Loop DO 23 20 19 16 15 8 7 0 0 0 0 0 0 1 1 0 0 0 a a a a a a 0 S 0 0 0 0 0 0 ABSOLUTE ADDRESS EXTENSION 23 20 19 16 15 8 7 0 0 0 0 0 0 1 1 0 i i...

Page 69: ... 1 1 0 0 no N0 N7 0 1 1 n n n A1 0 0 1 1 0 1 no M0 M7 1 0 0 m m m A 0 0 1 1 1 0 yes see Note 2 B 0 0 1 1 1 1 yes see Note 2 where rrr Rn register where nnn Nn register where mmm Mn register Note 1 For DO SP expr The actual value that will be loaded into the loop counter LC is the value of the stack pointer SP before the execution of the DO instruction incre mented by 1 Thus if SP 3 the execution o...

Page 70: ...e scaling mode bits in the status register If the data out of the shifter indi cates that the accumulator extension is in use the 24 bit data is limited to a maximum positive or negative saturation constant The shifted and limited value is loaded into LC although A or B remain unchanged Timing 6 mv oscillator clock cycles Memory 2 program words DO Start Hardware Loop DO Freescale Semiconductor I F...

Page 71: ...ntroller registers the ENDDO instruction must not be immediately preceded by any of the following instructions Immediately before ENDDO MOVEC to LA LC SR SSH SSL or SP MOVEM to LA LC SR SSH SSL or SP MOVEP to LA LC SR SSH SSL or SP MOVEC from SSH MOVEM from SSH MOVEP from SSH ORI MR ANDI MR Also the ENDDO instruction cannot be the last LA instruction in a DO loop Example DO Y0 NEXT exec loop endin...

Page 72: ...desired a JMP instruction i e JMP NEXT as previously shown must be included after the ENDDO instruction to transfer program control to the first instruction past the end of the DO loop Condition Codes The condition codes are not affected by this instruction Instruction Format ENDDO Opcode Instruction Fields None Timing 2 oscillator clock cycles Memory 1 program word MR CCR 15 14 13 12 11 10 9 8 7 ...

Page 73: ... the value 000003 and the 56 bit B accumulator contains the value 00 000005 000000 The EOR Y1 B instruction logically exclusive ORs the 24 bit value in the Y1 register with bits 47 24 of the B accumulator B1 and stores the result in the B accumulator with bits 55 48 and 23 0 unchanged Condition Codes I Set if data limiting has occurred during parallel move N Set if bit 47 of A or B result is set Z...

Page 74: ...X0 0 0 A 0 X1 1 0 B 1 Y0 0 1 Y1 1 1 Timing 2 mv oscillator clock cycles Memory 1 mv program words 23 8 7 4 3 0 DATA BUS MOVE FIELD 0 1 J J d 0 1 1 OPTIONAL EFFECTIVE ADDRESS EXTENSION EOR Logical Exclusive OR EOR Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 75: ...GAL instruction is in a DO loop at LA and the instruction at LA 1 is being inter rupted then LC will be decremented twice due to the same mechanism that causes LC to be decremented twice if JSR REP etc are located at LA This is why JSR REP etc at LA are restricted Clearly restrictions cannot be imposed on illegal instructions Since REP is uninterruptable repeating an ILLEGAL instruction results in...

Page 76: ...Fields None Timing 8 oscillator clock cycles Memory 1 program word 23 16 15 8 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 ILLEGAL Illegal Instruction Interrupt ILLEGAL Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 77: ...used The 12 bit data is zero extended to form the effective address See A 8 INSTRUCTION SEQUENCE RESTRICTIONS for restrictions The term cc may specify the following conditions cc Mnemonic Condition CC HS carry clear higher or same C 0 CS LO carry set lower C 1 EC extension clear E 0 EQ equal Z 1 ES extension set E 1 GE greater than or equal N V 0 GT greater than Z N V 0 LC limit clear L 0 LE less ...

Page 78: ...ter R4 are predecremented by 1 and the resulting address is then loaded into the pro gram counter PC if the specified condition is true If the specified condition is not true no jump is taken and the program counter is incremented by one Condition Codes The condition codes are not affected by this instruction Instruction Format Jcc xxx Opcode Jcc Jump Conditionally Jcc MR CCR 15 14 13 12 11 10 9 8...

Page 79: ... program words Instruction Format Jcc ea Opcode Instruction Fields cc 4 bit condition code CCCC ea 6 bit Effective Address MMMRRR Effective Addressing Mode M M M R R R Rn Nn 0 0 0 r r r Rn Nn 0 0 1 r r r Rn 0 1 0 r r r Rn 0 1 1 r r r Rn 1 0 0 r r r Rn Nn 1 0 1 r r r Rn 1 1 1 r r r Absolute Address 1 1 0 0 0 0 where rrr refers to an address register R0 R7 Jcc Jump Conditionally Jcc 23 16 15 8 7 0 O...

Page 80: ...0 0 1 0 EQ 1 0 1 0 PL 0 0 1 1 MI 1 0 1 1 NN 0 1 0 0 NR 1 1 0 0 EC 0 1 0 1 ES 1 1 0 1 LC 0 1 1 0 LS 1 1 1 0 GT 0 1 1 1 LE 1 1 1 1 Timing 4 jx oscillator clock cycles Memory 1 ea program words Jcc Jump Conditionally Jcc Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 81: ...from 0 23 If the specified memory bit is not clear the program counter PC is incremented and the absolute address in the extension word is ignored However the address register specified in the effective address field is always updated independently of the state of the nth bit All address reg ister indirect addressing modes may be used to reference the source operand S Abso lute Short and I O Short...

Page 82: ...struction Fields n bit number bbbbb ea 6 bit Effective Address MMMRRR xxxx 16 bit Absolute Address in extension word Effective Addressing Mode M M M R R R Memory SpaceS Bit Number bbbbb Rn Nn 0 0 0 r r r X Memory 0 00000 Rn Nn 0 0 1 r r r Y Memory 1 Rn 0 1 0 r r r Rn 0 1 1 r r r Rn 1 0 0 r r r 10111 Rn Nn 1 0 1 r r r Rn 1 1 1 r r r where rrr refers to an address register R0 R7 Timing 6 jx oscillat...

Page 83: ...000000 X Memory 0 00000 Y Memory 1 10111 111111 Timing 6 jx oscillator clock cycles Memory 2 program words Instruction Format JCLR n X pp xxxx JCLR n Y pp xxxx Opcode 23 16 15 8 7 0 ABSOLUTE ADDRESS EXTENSION 0 0 0 0 1 0 1 0 0 0 a a a a a a 1 S 0 b b b b b JCLR Jump if Bit Clear JCLR 23 16 15 8 7 0 ABSOLUTE ADDRESS EXTENSION 0 0 0 0 1 0 1 0 1 0 p p p p p p 1 S 0 b b b b b Freescale Semiconductor I...

Page 84: ...stination Register D D D D D D Bit Number bbbbb 4 registers in Data ALU 0 0 0 1 D D 00000 8 accumulators in Data ALU 0 0 1 D D D 8 address registers in AGU 0 1 0 T T T 10111 8 address offset registers in AGU 0 1 1 N N N 8 address modifier registers in AGU 1 0 0 F F F 8 program controller registers 1 1 1 G G G See A 9 INSTRUCTION ENCODING and Table A 18 for specific register encodings Timing 6 jx o...

Page 85: ...ictions A JMP instruction used within a DO loop cannot begin at the address LA within that DO loop A JMP instruction cannot be repeated using the REP instruction Example JMP R1 N1 jump to program address P R1 N1 Explanation of Example In this example program execution is transferred to the pro gram address P R1 N1 Condition Codes The condition codes are not affected by this instruction JMP Jump JM...

Page 86: ... 0 0 r r r Rn Nn 0 0 1 r r r Rn 0 1 0 r r r Rn 0 1 1 r r r Rn 1 0 0 r r r Rn Nn 1 0 1 r r r Rn 1 1 1 r r r Absolute address 1 1 0 0 0 0 where rrr refers to an address register R0 R7 Timing 4 jx oscillator clock cycles Memory 1 ea program words JMP Jump JMP 23 16 15 8 7 0 0 0 0 0 1 1 0 0 0 0 0 0 a a a a a a a a a a a a 23 16 15 8 7 0 0 0 0 0 1 0 1 0 1 1 M M M R R R 1 0 0 0 0 0 0 0 OPTIONAL EFFECTIV...

Page 87: ...ld is always updated independently of the specified condition All memory alterable addressing modes may be used for the effective address A fast short jump addressing mode may also be used The 12 bit data is zero extended to form the effective address The term cc may specify the following conditions cc Mnemonic Condition CC HS carry clear higher or same C 0 CS LO carry set lower C 1 EC extension c...

Page 88: ...e limit bit is set L 1 Both the return address PC and the status register SR are pushed onto the system stack prior to transferring program control to the subroutine if the specified condition is true If the specified condition is not true no jump is taken and the program counter is incremented by 1 Condition Codes The condition codes are not affected by this instruction Instruction Format JScc xx...

Page 89: ...ing Mode M M M R R R Mnemonic C C C C Mnemonic C C C C Rn Nn 0 0 0 r r r CC HS 0 0 0 0 CS LO 1 0 0 0 Rn Nn0 0 0 1 r r r GE 0 0 0 1 LT 1 0 0 1 Rn 0 1 0 r r r NE 0 0 1 0 EQ 1 0 1 0 Rn 0 1 1 r r r PL 0 0 1 1 MI 1 0 1 1 Rn 1 0 0 r r r NN 0 1 0 0 NR 1 1 0 0 Rn Nn 1 0 1 r r r EC 0 1 0 1 ES 1 1 0 1 Rn 1 1 1 r r r LC 0 1 1 0 LS 1 1 1 0 Absolute address 1 1 0 0 0 0 GT 0 1 1 1 LE 1 1 1 1 where rrr refers to...

Page 90: ... extension word if the nth bit of the source operand S is clear The bit to be tested is selected by an immediate bit number from 0 23 If the nth bit of the source operand S is clear the address of the instruction immediately following the JSCLR instruction PC and the system status register SR are pushed onto the system stack Program execution then continues at the specified absolute address in the...

Page 91: ...EP instruction Example JSCLR 1 Y FFE3 1357 go sub at P 1357 if bit 1 in Y FFE3 is clear Explanation of Example In this example program execution is transferred to the sub routine at absolute address P 1357 in program memory if bit 1 of the external I O loca tion Y FFE3 is a zero If the specified bit is not clear no jump is taken and the program counter PC is incremented by 1 Condition Codes The co...

Page 92: ... r r r where rrr refers to an address register R0 R7 Timing 6 jx oscillator clock cycles Memory 2 program words Instruction Format JSCLR n X aa xxxx JSCLR n Y aa xxxx Opcode Instruction Fields n bit number bbbbb aa 6 bit Absolute Short Address aaaaaa xxxx 16 bit Absolute Address in extension word 23 16 15 8 7 0 ABSOLUTE ADDRESS EXTENSION 0 0 0 0 1 0 1 1 0 1 M M M R R R 1 S 0 b b b b b JSCLR Jump t...

Page 93: ...ber bbbbb pp 6 bit I O Short Address pppppp xxxx 16 bit Absolute Address in extension word I O Short Address aaaaaa Memory SpaceS Bit Number bbbbb 000000 X Memory 0 00000 Y Memory 1 10111 111111 Timing 6 jx oscillator clock cycles Memory 2 program words JSCLR Jump to Subroutine if Bit Clear JSCLR 23 16 15 8 7 0 ABSOLUTE ADDRESS EXTENSION 0 0 0 0 1 0 1 1 1 0 p p p p p p 1 S 0 b b b b b Freescale Se...

Page 94: ... in AGU 0 1 0 T T T 10111 8 address offset registers in AGU 0 1 1 N N N 8 address modifier registers in AGU 1 0 0 F F F 8 program controller registers 1 1 1 G G G See A 9 INSTRUCTION ENCODING and Table A 18 for specific register encodings Timing 6 jx oscillator clock cycles Memory 2 program words 23 16 15 8 7 0 ABSOLUTE ADDRESS EXTENSION 0 0 0 0 1 0 1 1 1 1 D D D D D D 0 0 0 b b b b b JSCLR Jump t...

Page 95: ... specified memory bit is not set the program counter PC is incremented and the absolute address in the extension word is ignored However the address register specified in the effective address field is always updated independently of the state of the nth bit All address reg ister indirect addressing modes may be used to reference the source operand S Abso lute short and I O short addressing modes ...

Page 96: ...Opcode Instruction Fields n bit number bbbbb ea 6 bit Effective Address MMMRRR xxxx 16 bit Absolute Address in extension word Effective Addressing Mode M M M R R R Memory SpaceS Bit Number bbbbb Rn Nn 0 0 0 r r r X Memory 0 00000 Rn Nn 0 0 1 r r r Y Memory 1 Rn 0 1 0 r r r Rn 0 1 1 r r r Rn 1 0 0 r r r 10111 Rn Nn 1 0 1 r r r Rn 1 1 1 r r r where rrr refers to an address register R0 R7 MR CCR 15 1...

Page 97: ...Memory SpaceS Bit Number bbbbb 000000 X Memory 0 00000 Y Memory 1 10111 111111 Timing 6 jx oscillator clock cycles Memory 2 program words Instruction Format JSET n X pp xxxx JSET n Y pp xxxx Opcode 23 16 15 8 7 0 ABSOLUTE ADDRESS EXTENSION 0 0 0 0 1 0 1 0 0 0 a a a a a a 1 S 1 b b b b b JSET Jump if Bit Set JSET 23 16 15 8 7 0 ABSOLUTE ADDRESS EXTENSION 0 0 0 0 1 0 1 0 1 0 p p p p p p 1 S 1 b b b ...

Page 98: ...estination Register D D D D D D Bit Number bbbbb 4 registers in Data ALU 0 0 0 1 D D 00000 8 accumulators in Data ALU 0 0 1 D D D 8 address registers in AGU 0 1 0 T T T 10111 8 address offset registers in AGU 0 1 1 N N N 8 address modifier registers in AGU 1 0 0 F F F 8 program controller registers 1 1 1 G G G See A 9 Instruction Encoding and Table A 18 for specific register encodings Timing 6 jx ...

Page 99: ...is zero extended to form the effective address Restrictions A JSR instruction used within a DO loop cannot specify the loop address LA as its target A JSR instruction used within a DO loop cannot begin at the address LA within that DO loop A JSR instruction cannot be repeated using the REP instruction Example JSR R5 jump to subroutine at R5 update R5 Explanation of Example In this example program ...

Page 100: ...r r Rn Nn 0 0 1 r r r Rn 0 1 0 r r r Rn 0 1 1 r r r Rn 1 0 0 r r r Rn Nn 1 0 1 r r r Rn 1 1 1 r r r Absolute address 1 1 0 0 0 0 where rrr refers to an address register R0 R7 Timing 4 jx oscillator clock cycles Memory 1 ea program words 23 16 15 8 7 0 0 0 0 0 1 1 0 1 0 0 0 0 a a a a a a a a a a a a JSR Jump to Subroutine JSR 23 16 15 8 7 0 OPTIONAL EFFECTIVE ADDRESS EXTENSION 0 0 0 0 1 0 1 1 1 1 M...

Page 101: ...e source operand S is set The bit to be tested is selected by an immediate bit number from 0 23 If the nth bit of the source operand S is set the address of the instruction immediately following the JSSET instruction PC and the system status register SR are pushed onto the system stack Program execution then continues at the specified absolute address in the instruc tion s 24 bit extension word If...

Page 102: ...le In this example program execution is transferred to the sub routine at absolute address P 0100 in program memory if bit 23 of Y memory location Y 003F is a one If the specified bit is not set no jump is taken and the program counter PC is incremented by 1 Condition Codes The condition codes are not affected by this instruction Instruction Format JSSET n X ea xxxx JSSET n Y ea xxxx Opcode JSSET ...

Page 103: ...llator clock cycles Memory 2 program words Instruction Format JSSET n X aa xxxx JSSET n Y aa xxxx Opcode Instruction Fields n bit number bbbbb aa 6 bit Absolute Short Address aaaaaa xxxx 16 bit Absolute Address in extension word Absolute Short Address aaaaaa Memory SpaceS Bit Number bbbbb 000000 X Memory 0 00000 Y Memory 1 10111 111111 Timing 6 jx oscillator clock cycles Memory 2 program words JSS...

Page 104: ...ion word I O Short Address pppppp Memory SpaceS Bit Number bbbbb 000000 X Memory 0 00000 Y Memory 1 10111 111111 Timing 6 jx oscillator clock cycles Memory 2 program words 23 16 15 8 7 0 ABSOLUTE ADDRESS EXTENSION 0 0 0 0 1 0 1 1 1 0 p p p p p p 1 S 1 b b b b b JSSET Jump to Subroutine if Bit Set JSSET Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to...

Page 105: ...s in AGU 0 1 0 T T T 10111 8 address offset registers in AGU 0 1 1 N N N 8 address modifier registers in AGU 1 0 0 F F F 8 program controller registers 1 1 1 G G G See A 9 Instruction Encoding and Table A 18 for specific register encodings Timing 6 jx oscillator clock cycles Memory 2 program words 23 16 15 8 7 0 ABSOLUTE ADDRESS EXTENSION 0 0 0 0 1 0 1 0 1 1 D D D D D D 0 0 1 b b b b b JSSET Jump ...

Page 106: ...one bit to the left set up R0 Explanation of Example Prior to execution the 56 bit B accumulator contains the value 00 F01234 13579B The execution of the LSL B instruction shifts the 24 bit value in the B1 register one bit to the left and stores the result back in the B1 register Condition Codes L Set if data limiting has occurred during parallel move N Set if bit 47 of A or B result is set Z Set ...

Page 107: ...d A 0 B 1 Timing 2 mv oscillator clock cycles Memory 1 mv program words 23 8 7 4 3 0 DATA BUS MOVE FIELD 0 0 1 1 d 0 1 1 OPTIONAL EFFECTIVE ADDRESS EXTENSION LSL Logical Shift Left LSL Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 108: ...n the 56 bit A accumulator contains the value 37 444445 828180 The execution of the LSR A instruction shifts the 24 bit value in the A1 register one bit to the right and stores the result back in the A1 register Condition Codes L Set if data limiting has occurred during parallel move N Always cleared Z Set if bits 47 24 of A or B result are zero V Always cleared C Set if bit 24 of A or B was set p...

Page 109: ... A 0 B 1 Timing 2 mv oscillator clock cycles Memory 1 mv program words 23 8 7 4 3 0 DATA BUS MOVE FIELD 0 0 1 0 d 0 1 1 OPTIONAL EFFECTIVE ADDRESS EXTENSION LSR Logical Shift Right LSR Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 110: ...on of Example Prior to execution the 16 bit address register R0 contains the value 0003 the 16 bit address register N0 contains the value 0005 and the 16 bit address register R1 contains the value 0004 The execution of the LUA R0 N0 R1 instruction adds the contents of the R0 register to the contents of the N0 register and stores the resulting updated address in the R1 address register Note that no...

Page 111: ...R0 R7 0 n n n Rn Nn 0 0 1 r r r N0 N7 1 n n n Rn 0 1 0 r r r Rn 0 1 1 r r r where rrr refers to a source address register R0 R7 where nnn refers to a destination address register R0 R7 or N0 N7 Timing 4 oscillator clock cycles Memory 1 program word 23 16 15 8 7 0 0 0 0 0 0 1 0 0 0 1 0 M M R R R 0 0 0 1 d d d d LUA Load Updated Address LUA Freescale Semiconductor I Freescale Semiconductor Inc For M...

Page 112: ...gned value in the X0 register and adds the resulting 48 bit product to the 56 bit A accumulator X0 X0 lA 0 145227144519197 approximately 00 1296CD 9619C8 A Condition Codes L Set if limiting parallel move or overflow has occurred in result E Set if the signed integer portion of A or B result is in use U Set if A or B result is unnormalized N Set if bit 55 of A or B result is set Z Set if A or B res...

Page 113: ...1 Y0 1 1 0 Y1 X1 1 1 1 Note Only the indicated S1 S2 combinations are valid X1 X1 and Y1 Y1 are not valid Timing 2 mv oscillator clock cycles Memory 1 mv program words 23 8 7 4 3 0 DATA BUS MOVE FIELD 1 Q Q Q d k 1 0 OPTIONAL EFFECTIVE ADDRESS EXTENSION MAC Signed Multiply Accumulate MAC Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale ...

Page 114: ...e next instruction The upper portion of the accumulator A1 or B1 contains the rounded result which may be read out to the data buses Refer to the RND instruction for more complete information on the convergent rounding process Example MACR X0 Y0 B B X0 Y R4 N4 Y0 X0 Y0 B B rnd B update X0 Y0 R4 Explanation of Example Prior to execution the 24 bit X0 register contains the value 123456 0 142222166 t...

Page 115: ...omplete details Instruction Format MACR S1 S2 D MACR S2 S1 D Opcode Instruction Fields S1 S2 Q Q Q Sign k D d X0 X0 0 0 0 0 A 0 Y0 Y0 0 0 1 1 B 1 X1 X0 0 1 0 Y1 Y0 0 1 1 X0 Y1 1 0 0 Y0 X0 1 0 1 X1 Y0 1 1 0 Y1 X1 1 1 1 Note Only the indicated S1 S2 combinations are valid X1 X1 and Y1 Y1 are not valid Timing 2 mv oscillator clock cycles Memory 1 mv program words MR CCR 15 14 13 12 11 10 9 8 7 6 5 4 ...

Page 116: ...rmed with error detection since the L bit in the condition code register is latched When a 56 bit accumulator A or B is specified as a destination operand D any 24 bit source data to be moved into that accumulator is automatically extended to 56 bits by sign extending the MS bit of the source operand bit 23 and appending the source oper and with 24 LS zeros Similarly any 48 bit source data to be l...

Page 117: ...omatic zeroing Condition Codes L Set if data limiting has occurred during parallel move Instruction Format MOVE S D Opcode Instruction Fields See Parallel Move Descriptions for data bus move field encoding Timing 2 mv oscillator clock cycles Memory 1 mv program words MR CCR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LF T S1 S0 I1 I0 L E U N Z V C 23 8 7 4 3 0 DATA BUS MOVE FIELD 0 0 0 0 0 0 0 0 OPTIONA...

Page 118: ...u lator register A1 A0 B1 or B0 is specified as a source operand instead of the full 56 bit accumulator A or B This limiting feature allows block floating point operations to be performed with error detection since the L bit in the condition code register is latched When a 56 bit accumulator A or B is specified as a destination operand D any 24 bit source data to be moved into that accumulator is ...

Page 119: ... add X0 to A no parallel move Explanation of Example This is an example of an instruction which allows parallel moves but does not have one Condition Codes The condition codes are not affected by this type of parallel move Instruction Format Opcode Instruction Format defined by instruction Timing mv oscillator clock cycles Memory mv program words No Parallel Data Move MR CCR 15 14 13 12 11 10 9 8 ...

Page 120: ... same accumulator or portion of that accumulator may not be specified as a destination D in the parallel data bus move operation Thus if the opcode operand portion of the instruction specifies the 56 bit A accumulator as its desti nation the parallel data bus move portion of the instruction may not specify A0 A1 A2 or A as its destination D Similarly if the opcode operand portion of the instructio...

Page 121: ...rmat xx D Opcode Instruction Fields xx 8 bit Immediate Short Data iiiiiiii D D D d d d d d Sign Ext Zero X0 0 0 1 0 0 no no X1 0 0 1 0 1 no no Y0 0 0 1 1 0 no no Y1 0 0 1 1 1 no no A0 0 1 0 0 0 no no B0 0 1 0 0 1 no no A2 0 1 0 1 0 no no B2 0 1 0 1 1 no no A1 0 1 1 0 0 no no B1 0 1 1 0 1 no no A 0 1 1 1 0 A2 A0 B 0 1 1 1 1 B2 B0 R0 R7 1 0 r r r N0 N7 1 1 n n n where rrr Rn number where nnn Nn numb...

Page 122: ...d as a source S in the parallel data bus move operation This allows data to be moved in the same instruction in which it is being used as a source operand by a data ALU operation That is duplicate sources are allowed within the same instruction When a 24 bit source operand is moved into a 16 bit destination register the 16 LS bits of the 24 bit source operand are stored in the 16 bit destination r...

Page 123: ...ortion of the instruction Y1 N5 moves the 16 LS bits of the 24 bit value in the Y1 register into the 16 bit N5 register Condition Codes L Set if data limiting has occurred during parallel move N5 N5 0000 1234 Before Execution After Execution Y1 Y1 001234 001234 R Register to Register Data Move R MR CCR 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LF T S1 S0 I1 I0 L E U N Z V C Freescale Semiconductor I F...

Page 124: ...A2 0 1 0 1 0 no no no B2 0 1 0 1 1 no no no A1 0 1 1 0 0 no no no B1 0 1 1 0 1 no no no A 0 1 1 1 0 yes A2 A0 B 0 1 1 1 1 yes B2 B0 R0 R7 1 0 r r r N0 N7 1 1 n n n where rrr Rn number where nnn Nn number Timing mv oscillator clock cycles Memory mv program words 23 16 15 8 7 0 0 0 1 0 0 0 e e e e e d d d d d INSTRUCTION OPCODE R Register to Register Data Move R Freescale Semiconductor I Freescale S...

Page 125: ...MOTOROLA DSP56000 DSP56001 USER S MANUAL A 125 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 126: ...A 126 DSP56000 DSP56001 USER S MANUAL MOTOROLA Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

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