DSP56F807EVM Configuration Jumpers
Introduction
1-3
Figure 1-2. DSP56F807EVM Jumper Reference
Table 1-1. DSP56F807EVM Default Jumper Options
Jumper
Group
Comment
Jumpers
Connections
JG1
Primary UNI-3 Phase A Over-Current Selected for FAULTA1
1–2
JG2
Secondary UNI-3 Phase A Over-Current Selected for FAULTB1
1–2
JG3
CAN termination unselected
NC
JG4
Enable on-board Parallel JTAG Host/Target Interface
NC
JG5
Use on-board EXTAL crystal input for DSP oscillator
2–3
JG6
Use on-board XTAL crystal input for DSP oscillator
1–2
JG7
Selects DSP’s Mode 0 operation upon exit from reset
1-2
JG8
Enable on-board SRAM
1–2
JG9
Disable RS-232 output
NC
JG10
Secondary UNI-3 3-Phase Current Sense Selected as inputs to A/D
2–3, 5–6 & 8–9
JG11
Secondary UNI-3 serial selected
1–2, 3–4, 5–6 & 7–8
JG12
Primary Encoder Input Selected
2–3, 5–6 & 8–9
JG13
Secondary Encoder Input Selected
2–3, 5–6 & 8–9
JG14
Primary UNI-3 3-Phase Current Sense Selected as inputs to A/D
2–3, 5–6 & 8–9
JG15
Primary UNI-3 serial selected
1–2, 3–4, 5–6 & 7–8
JG16
PD0 input selected as a high input
1–2
JG17
PD1 input selected as a high input
1–2
JG8
DSP56F807EVM
JG
1
5
J3
JTAG
JG14
1
P3
USER
S/N
LED3
P1
Y1
U1
U2
S2
S3
3
1
2
JG13
S1
S4
S5
S6
P2
PWM
4
7
JG12
1
3
2
JG13
1
3
2
J4
J5
JG17JG16
JG6
JG8
U9
JG11
RESET
IRQB
IRQA
RUN/STOP
GP2
GP1
1
2
7
8
JG
15
1
2
7
8
JG11
3
1
2
JG12
3
1
4
JG14
6
9
7
JG9
JG2
JG3
JG4
JG6
JG10
1
3
2
JG4
JG5
JG1
JG9
JG7
J1
J2
1
JG16
3
1
JG17
3
3
1
2
JG10
1
JG2
3
1
JG1
3
JG7
JG3
1
JG5
3
Summary of Contents for Digital DNA DSP56F807
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Page 53: ... DSP56F807EVM Schematics A 1 Appendix A DSP56F807EVM Schematics ...
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