Mitsubishi V19-V21, Tehnical Manual

Page: 35 / 71

6-5
IC, IC7A02, generates a delayed reset pulse when
power is applied.
IC7A02 is a Reset Watchdog type of IC. When the
µPC is functioning, pulses are output at pin 73 of
IC7A00. The pulses constantly reset the counter in
IC7A02 and no Reset pulse is generated.
If lock up occurs, no pulses are generated at pin 73.
With no pulses from the TV µPC the counter in
IC7A02 is not reset and a Reset pulse is generated.
The same type of Reset action resets in the DM µPC
circuit.
If communication is
lost from either the
TV µPC or from the
DM µPC, the other
µPC automatically
generates a Reset
pulse. A Low at pin
11 of IC7A00 resets
the DM µPC, and a
Low from pin 10 of
the DB connector re-
sets the TV µPC.
Both Reset commands are routed through IC7B80, that
functions basically as an AND gate. This enables the
front panel Manual Reset button to Reset both µPCs.
V-CHIP Blocking Circuitry
The V-Chip Blocking circuitry allows blocking of
specific type of programming. Program rating in-
formation is located on line 21 of the TV signal. The
circuit configurations is not new but is presented here
as a reference.