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MELSEC-Q
4 SEQUENCE PROGRAM CONFIGURATION AND EXECUTION
CONDITIONS
3) Interruption during a network refresh:
If an interrupt factor occurs during a network refresh operation, the
network refresh operation is suspended, and the interrupt program is
executed.
This means that "assurance of blocks in cyclic data at each station"
cannot be secured by using a device designated as a destination of
link refresh operation on the MELSECNET/H Network System. 3
Interrupt factor
Interrupt program
execution
Network refresh
execution
10ms
10ms
10ms
10ms
Network refresh operation is suspended,
and the interrupt program is executed.
Fig.4.4 Interruption during Network Refresh Operation
4) Interruption during END processing:
If an interrupt factor occurs during an END processing waiting period
when constant scan is performed, the interrupt program corresponding
to the factor will be executed.
(c) See Section 10.6.2 for details on index register processing when switching
to an interrupt program from a scan execution type program or low speed
execution type program.
(4) High speed execution of an interrupt program and overhead time
By default, High Performance model QCPU performs the following process when
executing an interrupt program:
• To hide and restore an index register. (See section 10.6.2)
• To hide and restore the file name of a file register in use.
The above-listed processes are not performed if "Execute at a High Speed" is selected at
the "PLC System" tab screen in the “(PLC) Parameter" dialog box.
This will make it possible to shorten the duration of overhead time required for
execution of an interrupt program.
OVERHEAD TIME (
s)
CPU TYPE
High speed execution is not selected
High speed execution is selected
Q02CPU
380
230
Q02HCPU, Q06HCPU,
Q12HCPU, Q25HCPU
165
100
REMARK
1: For details on the IMASK and EI instructions, refer to the "QCPU (Q
mode)/QnACPU Programming Manual (Common Instructions).
To execute interrupt programs I0 through I31 and I48 through I255, use an EI
instruction to enter the interrupt programs into an interrupt enabled status.
2: See Section 10.10 for details on the priority ranking of interrupt programs.
3: For assurance of station unit blocks in cyclic data, see the "MELECNET/H
Network System Reference Manual."