RTE-V831-PC
USER’S MANUAL (Rev. 2.00)
40
13.4.5. OUTB, OUTH, OUTW
<Format>
OUTB [[address] data]
OUTH [[address] data]
OUTW [[address] data]
Writes to an I/O register. The OUTB, OUTH, and OUTW commands access in byte, halfword, and
word units, respectively. If an address or data is omitted, the previous address or data is assumed.
<Example>
OUTH 2000 55AA
Writes the halfword 55AAH to the I/O register at 2000H.
13.4.6. DCTR Command
<Format>
DCTR [ALL]
Displays the contents of DCTR registers. There are 256 DCTR registers. Among these 256
registers, the contents of the registers whose valid bit is on are displayed except when ALL is
specified. If ALL is specified, the contents of all DCTR registers are displayed. The DCTR registers
are mapped on the I/O space f2000000h-f2000fffh.
13.4.7. ITCR Command
<Format>
ITCR [ALL]
Displays the contents of ICTR registers. There are 128 ICTR registers. Among these 128 registers,
the contents of the registers whose valid bit is on are displayed except when ALL is specified. If ALL
is specified, the contents of all ICTR registers are displayed. The ICTR registers are mapped on the
I/O space fa000000h-fa000fffh.
13.4.8. CMCR Command
<Format>
CMCR [=] VALUE
Specifies a value in the cache memory control register (CMCR).
13.4.9. SFR Command
<Format>
SFR [register-name [=data]]
When a register name is specified with data omitted, the data read from the register is displayed.
When a register name is specified, and data is specified after =, the data is written to the register.
The size of data is automatically determined according to the valid size of the specified register. For
details of the internal I/O registers, refer to the manual provided with the V831 CPU.
<Example 1>
SFR
A list of registers is displayed.
<Example 2>
SFR IMR
The contents of the IMR register are displayed.
<Example 3>
SFR IMR=55AA
Data 55AAH is written into the IMR register.
