Midas RTE-V831-PC, User Manual

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RTE-V831-PC USER’S MANUAL (Rev. 2.00)
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8.9. INTERRUPT CONTROLLER (PIC) (4500-D000H TO 4500-D018H)
The PIC mainly exercises interrupt-related control. The table below indicates the assignment of
registers.
With the RTE-V831-PC, INT0 of the PIC is connected to NMI or INTP03 of the V831 according to the
specification of NMI/INT3-. INT1 is connected to INTP02.
Data bus
Logical address Register
D7 D6 D5 D4 D3 D2 D1 D0
4500-D000H
P I C I N T 0 M
IM07 IM06 IM05 IM04 IM03 IM02 IM01 IM00
4500-D008H
P I C I N T 1 M
IM17 IM16 IM15 IM14 IM13 IM12 IM11 IM10
4500-D010H
P I C I N T R
IR7 IR6 IR5 IR4 IR3 IR2 IR1 IR0
4500-D018H
P I C I N T E N
0 0 0 NMI/
INT3-
0 0 1
NMIEN
The INT0M and INT1M registers mask interrupts applied to INT0 and INT1, respectively. When the
IM0x or IM1x bit is set to 1, the interrupt is enabled. When multiple bits are selected, each OR value
activates an interrupt.
The INTR register is an interrupt status register, for which 1 is read whenever there is an interrupt
request. This does not depend on the state of masking. To clear an edge interrupt request, the
corresponding bit of this register must be set to 1.
The table below indicates the interrupt source assigned to each bit of IM0[0..7], IM1[0..7], and IR[0..7].
IM0, IM1, IR Interrupt source Request level
0 Timer 0 (mode 2) Edge (rising)
1 Serial 0 Level (high)
2 Host (ISA communication) Level (low)
3 Time-over Level (low)
4 Timer 1 (mode 2) Edge (rising)
5 Serial 1 Level (high)
6 Parallel (printer) Level (high)
7 ISA-IRQ Level
The INTEN register enables or disables all interrupts.
NMIEN: Disables a non-maskable interrupt (NMI) by hardware. At this time, the NMI pin is high.
NMIEN NMI
0 Sets a mask. (Reset value)
1 Does not set a mask.
NMI/INTP3-: Specifies whether an INT0 interrupt is to be applied to NMI or INTP03.
NMI/INTP3- INT0
0 INTP03 (Reset value)
1 NMI
[Caution]
INT0 (NMI/INTP03) is used with the monitor. So, never modify the related registers. INT1 is
released, and can be used freely.