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RTE-V831-PC

USER’S MANUAL (Rev. 2.00)

REVISION HISTORY

Date

REV.

Chapter

Explanation of revision

Apr. 14 1997

1.02

First edition

Apr. 28 1998

2.00

5.19

8.3

8.9

A description of the use of the PARTNER monitor has been added.

Corrections have been made to the following descriptions:

JCPU-A, pin 26 (+3..3 V

→

+3.3 V), pin 98 (+5 V

→

GND)

Logical address in the table (BC00-0000H

→

4500-2000H)

Request levels listed in the interrupt source table

Summary of Contents for RTE-V831-PC

Page 1: ...RTE V831 PC USER S MANUAL Rev 2 00 RTE V831 PC USER S MANUAL Rev 2 00 Midas lab...

Page 2: ...First edition Apr 28 1998 2 00 5 19 8 3 8 9 A description of the use of the PARTNER monitor has been added Corrections have been made to the following descriptions JCPU A pin 26 3 3 V 3 3 V pin 98 5...

Page 3: ...S CONNECTOR JEXT 8 5 19 CPU CONNECTOR JCPU A JCPU B 9 6 CONNECTION WITH THE HOST PC 11 6 1 INSTALLATION ON THE ISA BUS 11 6 2 STANDALONE USE OF THE BOARD 11 7 HARDWARE REFERENCES 12 7 1 MEMORY AND I O...

Page 4: ...installation 36 13 2 SWITCH SETTING 36 13 2 1 SW1 Setting 36 13 2 2 SW2 Setting 37 13 3 MULTI MONITOR 38 13 3 1 Monitor Work RAM 38 13 3 2 Interrupt 38 13 3 3 Interrupt for Forced Break 38 13 3 4 _IN...

Page 5: ...ed at the time of purchase is stored Even when neither of the debuggers is purchased together with the RTE V831 PC they can be purchased at anytime subsequently 1 1 NUMERIC NOTATION This manual repres...

Page 6: ...io output channels are provided 4 BASIC SPECIFICATIONS Processor V831 CPU clock 100 MHz max Bus clock 33 MHz max Power consumption 5 V 2 0 A Memory EPROM 128 KB 64 K 16 bits 40 pin DIP 1 512K bytes ma...

Page 7: ...tandalone that is without being inserted in an ISA bus slot the board should be supplied with power from an external power supply by connecting it to the JPOWER connector The external power should be...

Page 8: ...voice recording TOVER Lights when a time out occurs FLBUSY Lights while the flash ROM is busy during a write operation erasure etc LED Indication 5 6 TEST PINS FOR ROM EMULATOR TP Test pins are used t...

Page 9: ...to hold 40 pin ROM chips to provide standard 128K bytes 64K 16 bits When the ROM chips used here are to be replaced their type should be 27C1024 27C2048 or 27C4096 and the access time should be 150 n...

Page 10: ...ectors are converted to the RS 232C level The figures and table below indicate the pin and signal arrangements of these connectors For the signals to be connected to the host the table indicates two m...

Page 11: ...16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 JPRT Pin Arrangement JPRT pin No Signal name JPRT pin No Signal name 1 STB 2 AUTO_FD 3 D0 4 ERROR 5 D1 6 INIT 7 D2 8 SELECT_IN 9 D3 10 GND 11 D4 12 GND 13 D5 14 G...

Page 12: ...A5 GND B5 GND A6 TRCDATA1 B6 GND A7 GND B7 GND A8 TRCDATA2 B8 GND A9 GND B9 GND A10 TRCDATA3 B10 GND A11 GND B11 GND A12 DDI B12 GND A13 GND B13 GND A14 DCK B14 GND A15 GND B15 GND A16 DMS B16 GND A1...

Page 13: ...12 17 D13 18 D14 19 D15 20 D16 21 D17 22 D18 23 D19 24 D20 25 D21 26 3 3V 27 GND 28 D22 29 D23 30 D24 31 3 3V 32 GND 33 D25 34 D26 35 D27 36 D28 37 D29 38 D30 39 D31 40 3 3V 41 GND 42 LLMWR 43 LUMWR 4...

Page 14: ...10 A22 111 DDO 112 DMS 113 DCK 114 DDI 115 TRCDATA3 116 TRCDATA2 117 TRCDATA1 118 TRCDATA0 119 CLKOUT 120 5V 121 GND 122 A21 123 A20 124 A19 125 A18 126 A17 127 A16 128 A15 129 A14 130 A13 131 A12 132...

Page 15: ...ce driver it is likely that the set I O address is the same as one already in use Check the I O address of the board by referring to the applicable manual of the PC or the board 5 When the system turn...

Page 16: ...Uncacheable area ICE reserve Uncacheable area CS4 space CS5 space CS6 space CS7 space EXT BUS SRAM mem area 4E00 0000 4E07 FFFF FE00 0000 FE07 FFFF DRAM mem area 0000 0000 00FF FFFF 4000 0000 40FF FF...

Page 17: ...Section 10 3 CS5 space x500 000 to x5FF FFFF xD00 000 to xDFF FFFF CS5 is the space for I O devices including the timer audio channels and serial and parallel channels mounted on the board The bus con...

Page 18: ...tting reference Low speed I O 4500 C000H to 4500 C007H ISA communication Not made available 4500 D000H to 4500 D01FH Interrupt controller setting reference Low speed I O 4580 0000H to 4580 001FH Audio...

Page 19: ...r D7 D6 D5 D4 D3 D2 D1 D0 4500 4000H CMD 0 initial value X X X X 0 0 0 0 0 0 0 0 8 5 COMMAND REGISTER 1 PORT 4500 4000H READ WRITE This port is used for exercising byte enable BHEn A0 control when acc...

Page 20: ...ed as UART PRINTER controller The TL16C552A provides two UART channels and one channel of the bidirectional printer port PS2 compatible It incorporates a 16 character FIFO buffer in the UART receive c...

Page 21: ...is connected to the PIC and used as the interval timer for the monitor A 2 MHz clock input is connected to channel 0 Channel 1 can be used by a user program as necessary It serves as the pre scale co...

Page 22: ...t The INTR register is an interrupt status register for which 1 is read whenever there is an interrupt request This does not depend on the state of masking To clear an edge interrupt request the corre...

Page 23: ...15 D14 D13 D12 D11 D10 D9 D8 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 4580 0010H MCLKDIV 0 0 0 DIV4 DIV3 DIV2 DIV1 DIV0 D15 D0 4580 2000H AUDIO DATA MSB L R channel voice data LSB The CONTROL register...

Page 24: ...erflow upon replay 0 No underflow detected 1 Underflow detected FF0 HF0 EF0 FIFO for replay 0 0 1 Empty 0 1 0 Half full 1 1 0 Full FIFO write disabled REX Recording status 0 Stopped 1 Being conducted...

Page 25: ...10 7 KHz 42 7 KB 1 0 0 0 1 2 587 MHz 10 1 KHz 40 4 KB 1 0 0 1 0 2 458 MHz 9 6 KHz 38 4 KB 1 0 0 1 1 2 341 MHz 9 1 KHz 36 6 KB 1 0 1 0 0 2 234 MHz 8 7 KHz 34 9 KB 1 0 1 0 1 2 137 MHz 8 3 KHz 33 4 KB 1...

Page 26: ...NT0 is used for the system used with the Multi monitor while INT1 is used for a user application Interrupt source Timer 0 mode 2 Serial 0 Host ISA communication Time over Timer 1 mode 2 Serial 1 Paral...

Page 27: ...st A DMA request for data to be written to the audio data buffer during replay A timeout results in an underrun error CH1 Recording request A DMA request for data to be read from the audio data buffer...

Page 28: ...Connector Pin Arrangement Signal name Input output Function A 1 19 Output Address bus signal connected to the CPU address signal via a buffer A0 BHE Output Byte low high enable signal D 0 15 Input out...

Page 29: ...gh T10 T11 T12 T13 T14 T15 T16 T17 T18 D out W rite cycle JEXT Bus Cycle Symbol Description Min ns Max ns T1 RD address setup time 0 T2 RD address hold time 0 T3 RD cycle time 50 T4 RD cycle interval...

Page 30: ...space mapping The EXT bus space is mapped onto the CS4 space of the V831 For access select memory or I O space with the bus controller BCTC built into the CPU 2 A0 and BHE signal handling The A0 and B...

Page 31: ...H 900EH Half word Approx 15 ms For detailed information about the registers refer to the manual provided with the V831 CPU 11 2 LIBRARIES Libraries are required for programming using the C compiler fo...

Page 32: ...ecovery InitTimer Timer initialization outb 0x4500B00C 0x74 IOWAIT Timer 1 set to mode 2 outb 0x4500B004 INTERVAL IOWAIT Lower digit count of timer 1 outb 0x4500B004 INTERVAL 256 IOWAIT Higher digit c...

Page 33: ...0x555 2 0xAA char addr2 0x2AA 2 0x55 char addr2 0x555 2 cmd return 0 static FlashDataPoll int addr int data Busy check int rdata data 0xff Byte do rdata char addr 0xff if data rdata BIT_DQ 7 0 break w...

Page 34: ...error saddr Next address daddr daddr DST_ADDR for i 0 i 4 i FlashRead daddr i Initialization End return err After running this program with the debugger terminate the program normally Next terminate t...

Page 35: ...kHz inh 0x45800010 Dummy read outh 0x45800000 0 Reset clear Set63310Reg 0 0 IN1L 0db Set63310Reg 1 0 IN1R 0db Set63310Reg 17 0 OUTDACL 0db Set63310Reg 18 0 OUTDACR 0db return 0 AudioTerm Audio termin...

Page 36: ...1 3 TM demand 1 1 DS half word 1 Enable outh 0x45800000 0x100 Start recording while inh DMA1 12 1 0 Wait for DMA termination outh 0x45800000 0 Recording termination return 0 define COUNT 0x10000 L R...

Page 37: ...rea is allocated at FE07 0000H to FE07 01FFH in SRAM So for an interrupt with exception code FE00H an instruction for causing a branch to the interrupt handling routine is to be written at address FE0...

Page 38: ...ated This is because the initial value of the alternate vector is an instruction for causing a branch to the break handling routine of the monitor ROM 2 If the relative address from an alternate vecto...

Page 39: ...program placed in the EI interrupt enable state is subject to single stepping an interrupt is accepted even during single stepping 3 After a break in the interrupt handling routine exiting from the i...

Page 40: ...be used to set up the evaluation board The switch layout is shown below Location of the Switches on the RTE V831 PC Board SW1 SW2 13 2 1 SW1 Setting SW1 is a switch for general purpose input ports For...

Page 41: ...rom EPROM Factory set Boot Time Bus Size and ROM Setting 13 2 2 SW2 Setting SW2 is a switch for selecting the I O address of the ISA bus Switches 1 to 8 correspond to ISA addresses A4 to A11 respectiv...

Page 42: ...ill occur if the user program uses an interrupt with a higher priority than INTP03 or if interrupts are disabled DMA operation is continued even during a break 13 3 4 _INIT_SP Setting _INIT_SP stack p...

Page 43: ...resentations are invalid 0x1234 1234H 1234 13 4 1 HELP Format HELP command name Displays a list of RTE commands and their formats A question mark can also be used in place of the character string HELP...

Page 44: ...TR registers There are 128 ICTR registers Among these 128 registers the contents of the registers whose valid bit is on are displayed except when ALL is specified If ALL is specified the contents of a...

Page 45: ...general purpose input ports For the PARTNER monitor in the factory installed ROM SW1 is used as shown below SW1 1 2 Baud rate Setting ON ON 115200 baud OFF ON 38400 baud ON OFF 19200 baud OFF OFF 9600...

Page 46: ...1 2 SW2 Setting SW2 is a switch for selecting the I O address of the ISA bus Switches 1 to 8 correspond to ISA addresses A4 to A11 respectively A12 to A15 are fixed at 0 This means that the I O addres...

Page 47: ...does not restart even upon reexecution When INTP03 is used No break will occur if the user program uses an interrupt with a higher priority than INTP03 or if interrupts are disabled DMA operation is c...

Page 48: ...RTE V831 PC USER S MANUAL Rev 2 00 44 Memo RTE V831 PC User s Manual M6A1MNL01 Midas lab...

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