USB5744
DS00001855E-page 34
2015-2017 Microchip Technology Inc.
9.6
AC Specifications
This section details the various AC timing specifications of the device.
9.6.1
POWER SUPPLY AND RESET_N SEQUENCE TIMING
illustrates the recommended power supply sequencing and timing for the device.
VDD33
should rise after or
at the same rate as
VDD12
. Similarly,
RESET_N
and/or
VBUS_DET
should rise after or at the same rate as
VDD33
.
VBUS_DET
and
RESET_N
do not have any other timing dependencies.
9.6.2
POWER-ON AND CONFIGURATION STRAP TIMING
illustrates the configuration strap valid timing requirements in relation to power-on, for applications where
RESET_N
is not used at power-on. In order for valid configuration strap values to be read at power-on, the following
timing requirements must be met. The operational levels (V
opp
) for the external power supplies are detailed in
9.2, "Operating Conditions**," on page 30
.
Device configuration straps are also latched as a result of
RESET_N
assertion. Refer to
Section 9.6.3, "Reset and Con-
for additional details.
FIGURE 9-2:
POWER SUPPLY AND RESET_N SEQUENCE TIMING
TABLE 9-5:
POWER SUPPLY AND RESET_N SEQUENCE TIMING
Symbol
Description
Min
Typ
Max
Units
t
VDD33
VDD12
to
VDD33
rise time
0
ms
t
reset
VDD33
to
RESET_N
/
VBUS_DET
rise time
0
ms
FIGURE 9-3:
POWER-ON CONFIGURATION STRAP VALID TIMING
TABLE 9-6:
POWER-ON CONFIGURATION STRAP LATCHING TIMING
Symbol
Description
Min
Typ
Max
Units
t
csh
Configuration strap hold after external power supplies at opera-
tional levels
1
ms
VDD12
VDD33
RESET_N/
VBUS_DET
All External
Power Supplies
V
opp
Configuration
Straps
t
csh
