Figure 4-25. e-MMC Interface Example Schematic
J10
K9
F5
E6
P3
P5
N4
C6
M4
C2
DAT0
DAT1
DAT2
DAT3
DAT4
DAT5
DAT6
DAT7
CMD
CLK
nRST
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSS1
VSS2
VSS3
VSS4
VSS5
VCC0
VCC1
VCC2
VCC3
VCCQ1
VCCQ2
VCCQ3
VCCQ4
VCCQ5
VDDI
C4
N5
K8
H10
E7
N2
P6
P4
G5
VDDSDHC
VDD_3V3
2.2uF
C
GND
0.1uF
C
2.2uF
C
GND
0.1uF
C
A3
A4
A5
B2
B3
B4
B5
B6
M5
M6
K5
VDDSDHC
10k
R
10k
R
10k
R
10k
R
10k
R
10k
R
10k
R
10k
R
10k
R
10k
R
ATSAMA5D27-WLSOM1
U1
PA5
163
PA1
162
PA0
165
PA2
166
PA3
164
PA10
168
PA4
169
PA6
171
PA9
172
PA8
167
PA7
173
4.6.2.2
Design Layout Recommendations
When designing the e-MMC interface, consider the following recommendations:
• Match signal lengths to within 50 mils. Affected PIOs in the example above are PA0 to PA9.
• Place the clock line (PA0) at least 3 times the trace width away from other signals for noise immunity.
• Place data signals at least 2 times the trace width away from any other data trace.
• Place data signals at least 1 trace width away from any copper plan.
Figure 4-26. e-MMC Layout Example
Clock
Trace
Data
Traces
Data
Traces
W
3W
W
3W
2W
W
2W
Copper
Plane
4.6.3
Interfacing with NAND Flash
This Static Memory Controller (SMC) is capable of handling several types of external memory and peripheral devices,
such as SRAM, PSRAM, PROM, EPROM, EEPROM, LCD module, NOR Flash and NAND Flash.
The SMC generates the signals that control the access to external memory devices or peripheral devices.
The SMC embeds a NAND Flash Controller (NFC). The NFC can handle automatic transfers, sending the commands
and address cycles to the NAND Flash and transferring the contents of the page (for read and write) to the NFC
SRAM. It minimizes the CPU overhead.
The SMC includes programmable hardware error correcting code with one-bit error correction capability and supports
two-bit error detection.
SAMA5D27 Wireless SOM1
Functional Description
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2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS60001590D-page 37
