4.2.2.2
Power Configurations: Multiple Supplies
Figure 4-8. ATSAMA5D27-WLSOM1 Multiple Supplies Connection Example
VDD_MAIN
VDD_3V3
VDDISC
VDDANA
VDDFUSE
VDD_DDR
VLDO2
ATSAMA5D27-WLSOM1
VDDSDHC
VDDBU
Input Supply
(3.0V - 5.5V)
Application Board
(1.8V)
Application Board
(1.8V to 3.3V)
Application Fuse
(2.5V)
LDO
(2.5V/2.8V/3.0V)
LDO + Switch
(3.3V/1.8V)
Backup
Battery
4.2.3
Power On/Off Sequences
4.2.3.1
LPDDR2 Power-Off Sequence
The LPDDR2 power-off sequence must be controlled by software to preserve the LPDDR2 device.
In this sequence, the CKE signal should be low during the full period the power rails are powering down.
The power failure can be controlled by the embedded Voltage Supervisor (MIC842) and handled at system level (IRQ
on PD31). The LPDDR2 power-off sequence is applied using the bit LPDDR2_LPDDR3_PWOFF in the MPDDRC
Low-Power register (MPDDRC_LPR).
For more information, refer to the following documents:
• SAMA5D2 Series Data sheet available on
, sections
LPDDR2 Power Fail Management
and
MPDDRC Low-Power Register
• Jedec Standard
Low Power Double Data Rate 2 (LPDDR2)
, JESD209-2B
Note:
An uncontrolled power-off sequence can be applied only up to 400 times in the life of an LPDDR2 device.
SAMA5D27 Wireless SOM1
Functional Description
©
2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS60001590D-page 27
