Microchip Technology ATSAMA5D27-WLSOM1, Manual

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4.2.3.3 Power ON/OFF Sequences for Multiple Supplies
Figure 4-11. ATSAMA5D27-WLSOM1 Multiple Supplies Connections: Power-On Sequence
SYSTEM STATUS BACKUP STARTUP POWER-UP NRST RELEASED SYSTEM BOOT I²C COMMAND VLDO2 POWER UP
VDDBU 1.65V TO 3.6V
VDD_MAIN 5.0V
nSTART_SOM
VDD_3V3
VDDANA
VDDSDHC 3.3V 1.8V
VDDISC
VDD_DDR
NRST
PMIC_I2C
VLDO2
t1
t2
t3
t4
t5
t6
a
b
c
d
e
f
g
h
Figure 4-12. ATSAMA5D27-WLSOM1 Multiple Supplies Connections: Power-Off Sequence
SYSTEM STATUS SYSTEM ON POWER-OFF REQUEST NRST ASSERTS SYSTEM OFF
VDD_MAIN 5.0V
VDDBU 1.65V to 3.6V
SHDN
VDD_3V3
VDDANA
VDDISC
VDDSDHC
VDD_DDR
NRST
PMIC_I2C
VLDO2
t8
t9
t7
a
b
c
d
e
f
Table 4-2. ATSAMA5D27-WLSOM1 Multiple Supplies Timing Table
Symbol Description Min. Typ. Max. Unit
t1 Power-Up Request Timing 0.5 – 2000 ms
t2 VDDSDHC Power-Up Timing – 35 100 µs
t3 VDDISC Power-Up Timing – 40 100 µs
t4 VDD_DDR Power-Up Timing – 8 – ms
t5 NRST Timing for Release – 16 – ms
t6 VLDO2 Power-Up Timing after I²C Request – 0.5 1 ms
t7 VLDO2 Power-Down Timing after I²C Request – – 1 ms
t8 VDD_3V3 Power-Down Timing – 10 – µs
t9 NRST Forced to Low Timing – – 10 µs
4.2.4 Baseboard Power Delivery Application Diagram Example
The following figure is an example of power architecture at the baseboard level, input to the SOM and output from the
SOM.
SAMA5D27 Wireless SOM1
Functional Description
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Complete Datasheet
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