3.2.4
PIOD Pin Description
Pad No. Power Rail
I/O Type
Primary
Alternate
PIO Peripheral
Reset State (Signal, Dir, PU, PD, HiZ, ST)
Note
Signal Dir
Signal
Dir Func
Signal
Dir IO Set
J7
VDD_3V3
GPIO_CLK
PD0
I/O
–
–
A
LCDPCK
O
2
PIO, I, PU, ST
B
FLEXCOM4_IO4
O
1
C
UTXD3
O
2
D
GTSUCOMP
O
2
F
A23
O
2
D8
VDD_3V3
GPIO
PD1
I/O
–
–
A
LCDDEN
O
2
PIO, I, PU, ST
D
GRXCK
I
2
F
A24
O
2
J6
VDD_3V3
GPIO_CLK
PD2
I/O
–
–
A
URXD1
I
1
PIO, I, PU, ST
D
GTXER
O
2
E
ISI_MCK
O
2
F
A25
O
2
M3
VDDANA
GPIO_AD
PD3
I/O PTC_ROW0
–
A
UTXD1
O
1
PIO, I, PU, ST
B
FIQ
I
2
D
GCRS
I
2
E
ISI_D11
I
2
F
NWAIT
I
2
L6
VDDANA
GPIO_AD
PD4
I/O PTC_ROW1
–
B
URXD2
I
1
PIO, I, PU, ST
Note (2)
D
GCOL
I
2
E
ISI_D10
I
2
F
NCS0
O
2
L2
VDDANA
GPIO_AD
PD5
I/O PTC_ROW2
–
B
UTXD2
O
1
PIO, I, PU, ST
Note (2)
D
GRX2
I
2
E
ISI_D9
I
2
F
NCS1
O
2
J1
VDDANA
GPIO_AD
PD6
I/O PTC_ROW3
–
A
TCK
I
2
PIO, I, PU, ST
Note (2)
D
GRX3
I
2
E
ISI_D8
I
2
F
NCS2
O
2
L5
VDDANA
GPIO_AD
PD7
I/O PTC_ROW4
–
A
TDI
I
2
PIO, I, PU, ST
Note (3)
D
GTX2
O
2
E
ISI_D0
I
2
F
NWR1/NBS1
O
2
SAMA5D27 Wireless SOM1
Pinout
©
2021 Microchip Technology Inc.
and its subsidiaries
Complete Datasheet
DS60001590D-page 16
