Microchip Technology ADM00732, User Manual

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HV7358DB1 GUI Operation

2020 Microchip Technology Inc. DS50002951A-page 35
3.4.8.13 OTP BIT
OTP is an I
2
C bit that signals an overtemperature condition inside the HV7358 part.
The flag is reset by the I
2
C reading of the ADDR = 01h register. If the overtemperature
event continues, the flag will be retriggered at the next EN rising edge. See Table 3-19 .
3.4.8.14 BFEN BIT
BFEN is the I
2
C bit that determines the output buffer enable when BSEL =
1
.
TABLE 3-19: BFEN FOR BSEL =
1
3.4.8.15 EOTC BIT
Determines when the RTZ+ and TRSW delay starts. If EOTC =
0
, the period starts
immediately after all channels are finished. If EOTC =
1
, the period starts at the first F
C
clock rising edge after ETI becomes high and after all channels finish the TX
CH
period.
3.4.8.16 SPIBC BIT
Enables the SPI Broadcast mode when SPISEL =
1
.
TABLE 3-20: SPIBC FOR SPISEL =
1
3.4.8.17
Manually Read
BUTTON
The
Manually Read
button will read and display the current values of the I
2
C registers.
FIGURE 3-12: I
2
C Parameter Read Back Window.
OTP Temperature
0
In Range
1
Overtemperature
SPIBC
0
Disabled
1
Enabled