Microchip Technology ADM00732, User Manual

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HV7358DB1
USER’S GUIDE

2020 Microchip Technology Inc. DS50002951A-page 47
Chapter 5. PCB Design and Layout Techniques
5.1 INTRODUCTION
The PCB layout techniques are a very important part of the ultrasound system design.
The HV7358DB1 generates high-voltage, high-current, high-frequency and high-speed
pulses. Proper PCB layout is required to optimize the waveforms.
5.1.1 High-Speed Trace, Grounding and Heatsinking PCB Design
Techniques
A solid GND plane must be created. It should be a solid copper layer, on Layer 2,
directly under HV7358.
To optimize heatsinking of the HV7358, use as many vias from V
SUB
, RGND and GND
to the GND plane as possible. These signals carry large currents. Their PCB traces
should be on the top layer; they should be as short as possible and have as many vias
as possible. Maximize the number of vias on all the power supply traces.
High-speed (200 MHz) PCB trace design practices should be used as a starting point.
The TX outputs are high-voltage and high-speed traces. V
PP
and V
NN
are high-voltage
and high-current traces. Additional trace spacing may be required for the high-voltage
traces. Also, any parasitic coupling from the HV7358 TX outputs to digital input signals
may cause error signals on the logic input pins. Adequate spacing and possible
isolation are required. Additional width is required for the high-current traces.
5.1.2 Bypass Caps
The V
LL
, V
DD
, V
GP
, V
GN
, V
PP
/1 and V
NN
/1 power supply pins, and the CPF0/1, CNF0/1,
CPOS and CNEG internal gate driver floating supply rails all require bypass capacitors.
All can draw fast transient currents of up to 2.8 Amperes each. X7R or X5R-type
capacitors, 1.0 to 2.2
μ F are recommended.They must be located as close to the
HV7358 pins as possible. PCB trace width should be capable of handling these
transients.
5.1.3 PCB Layout Techniques for TCKP/TCKN
The clock can be driven with a pair of LVDS connections or a single-ended clock.
For LVDS implementations, an 100
Ω differential termination resistor must be
connected as close as possible to the LVDS input pair.
LVDS clock traces on the PCB should be designed as two 50
Ω transmission lines with
respect to the GND plane. The differential traces should be as close as possible after
they leave the LVDS buffer IC.
With a single-ended clock, a 33
Ω series termination resistor is required for each buffer
output. These resistors should be as close to the clock buffer output pin as possible.
The clock trace on the PCB should be designed as a 50
Ω transmission line with respect
to the GND plane.