Microchip Technology ADM00732, User Manual

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HV7358DB1 GUI Operation
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2020 Microchip Technology Inc. DS50002951A-page 33
3.4.8.5 TRDLY[4:0] BITS
The TRDLY bits set the I
2
C T/R Switch On-Time Delay Selection Control register. The
TRDLY are a 5-bit binary word. The GUI accepts 0 to 31 in decimal. The actual delay
time is calculated from the equation:
EQUATION 3-7:
K
is determined by Table 3-12 .
3.4.8.6 PSEL BIT
PSEL is the I
2
C bit that determines if PLLEN or PEN controls the PLL enable.
TABLE 3-13: PSEL EFFECT
TABLE 3-12: TRDLY
D4 D3 D2 D1 D0 Decimal K
0 0 0 0 0
0 1
0 0 0 0 1
1 8
0 0 0 1 0
2 12
0 0 0 1 1
3 16
0 0 1 0 0
4 20
0 0 1 0 1
5 24
0 0 1 1 0
6 36
0 0 1 1 1
7 40
0 1 0 0 0
8 48
0 1 0 0 1
9 60
0 1 0 1 0
10 64
0 1 0 1 1
11 72
0 1 1 0 0
12 80
0 1 1 0 1
13 96
0 1 1 1 0
14 100
0 1 1 1 1
15 120
1 0 0 0 0
16 128
1 0 0 0 1
17 144
1 0 0 1 0
18 160
1 0 0 1 1
19 192
1 0 1 0 0
20 200
1 0 1 0 1
21 240
1 0 1 1 0
22 288
PSEL Controlling Signal
0
PEN
1
PLLEN
T
TRDLY
= K/F
C