MeiG Smart product technical information
SLM758
Hardware Design Guide
Page 42
Main screen interface
MIPI_DSI0_CLK_N
64
O
MIPI_LCD clock line
MIPI_DSI0_CLK_P
65
O
MIPI_DSI0_LANE0_N
189
I/O
MIPI_LCD data line
MIPI_DSI0_LANE0_P
190
I/O
MIPI_DSI0_LANE1_N
66
I/O
MIPI_DSI0_LANE1_P
67
I/O
MIPI_DSI0_LANE3_N
73
I/O
MIPI_DSI0_LANE3_P
74
I/O
MIPI_DSI0_LANE2_N
71
I/O
MIPI_DSI0_LANE2_P
72
I/O
GPIO61_LCD_RST_N
75
O
LCD reset pin
GPIO24_LCD_TE0
76
I/O
LCD frame sync signal
LCD_BL_LED_K1
5
AI
LCD series backlight negative
pole 1
LCD_BL_LED_K2
6
AI
LCD series backlight negative
pole 2
LCD_BL_LED_A
7
PO
LCD series backlight positive
pole
VREG_L6_1P8
139
O
1.8V power supply
VREG_L17_2P85
137
O
2.8V power supply
Secondary screen interface
MIPI_DSI1_CLK_N
242
O
MIPI_LCD2 clock line
MIPI_DSI1_CLK_P
241
O
MIPI_DSI1_LANE0_N
226
I/O
MIPI_LCD2 data line
MIPI_DSI1_LANE0_P
225
I/O
MIPI_DSI1_LANE1_N
240
I/O
MIPI_DSI1_LANE1_P
239
I/O
MIPI_DSI1_LANE2_N
244
I/O
MIPI_DSI1_LANE2_P
243
I/O
MIPI_DSI1_LANE3_N
246
I/O
MIPI_DSI1_LANE3_P
245
I/O
GPIO63_LCD2_RST_N
99
O
LCD2 reset pin
GPIO25_LCD_TE1
77
I/O
LCD2 frame sync signal
PM8953_MPP2
112
I/O
Screen backlight PWM control
VREG_L6_1P8
139
O
1.8V power supply
VREG_L17_2P85
137
O
2.8V power supply
LCD_ID of the module, this pin is internally GPIO. When used as LCD_ID, please confirm
