MeiG Smart product technical information
SLM758
Hardware Design Guide
Page 16
Main display interface (MIPI)
MIPI_DSI0_CLK_N
64
O
MIPI_LCD clock
MIPI_DSI0_CLK_P
65
O
MIPI_DSI0_LANE0_N
189
I/O
MIPI_LCD data
MIPI_DSI0_LANE0_P
190
I/O
MIPI_DSI0_LANE1_N
66
I/O
MIPI_DSI0_LANE1_P
67
I/O
MIPI_DSI0_LANE3_N
73
I/O
MIPI_DSI0_LANE3_P
74
I/O
MIPI_DSI0_LANE2_N
71
I/O
MIPI_DSI0_LANE2_P
72
I/O
GPIO61_LCD_RST_N
75
O
LCD reset
GPIO24_LCD_TE0
76
I/O
LCD frame sync signal
The main display backlight interface
LCD_BL_LED_K1
5
AI
LCD Series backlight negative1
Each normal
20mA
，
max
30mA
LCD_BL_LED_K2
6
AI
LCD Series backlight negative2
LCD_BL_LED_A
7
PO
LCD Series backlight positive
Sub display interface (MIPI)
MIPI_DSI1_CLK_N
242
O
MIPI_LCD2 clock
MIPI_DSI1_CLK_P
241
O
MIPI_DSI1_LANE0_N
226
I/O
MIPI_LCD2 data
MIPI_DSI1_LANE0_P
225
I/O
MIPI_DSI1_LANE1_N
240
I/O
MIPI_DSI1_LANE1_P
239
I/O
MIPI_DSI1_LANE2_N
244
I/O
MIPI_DSI1_LANE2_P
243
I/O
MIPI_DSI1_LANE3_N
246
I/O
MIPI_DSI1_LANE3_P
245
I/O
GPIO63_LCD2_RST_N
99
O
LCD2 reset
GPIO25_LCD_TE1
77
I/O
LCD2 frame sync signal
UART(1.8V)
UART2_MSM_TX
11
I
UART2 data transmit
UART2_MSM_RX
12
O
UART2 data receive
GPIO13_UART4_RX
16
O
UART4 data receive
GPIO12_UART4_TX
15
I
UART4 data transmit
GPIO17_UART5_RX
255
O
UART5 data receive
