Special-Purpose Registers
The DS3232 has two additional registers (control and
control/status) that control the real-time clock, alarms,
and square-wave output.
Control Register (0Eh)
Bit 7: Enable Oscillator (
EOSC
).
When set to logic 0,
the oscillator is started. When set to logic 1, the oscilla-
tor is stopped when the DS3232 switches to battery
power. This bit is clear (logic 0) when power is first
applied. When the DS3232 is powered by V
CC
, the
oscillator is always on regardless of the status of the
EOSC
bit. When
EOSC
is disabled, all register data is
static.
Bit 6: Battery-Backed Square-Wave Enable
(BBSQW).
When set to logic 1 with INTCN = 0 and V
CC
< V
PF
, this bit enables the square wave. When BBSQW
is logic 0, the
INT
/SQW pin goes high impedance when
V
CC
< V
PF
. This bit is disabled (logic 0) when power is
first applied.
Bit 5: Convert Temperature (CONV).
Setting this bit to
1 forces the temperature sensor to convert the temper-
ature into digital code and execute the TCXO algorithm
to update the capacitance array to the oscillator. This
can only happen when a conversion is not already in
progress. The user should check the status bit BSY
before forcing the controller to start a new TCXO exe-
cution. A user-initiated temperature conversion does
not affect the internal 64-second (default interval)
update cycle.
A user-initiated temperature conversion does not affect
the BSY bit for approximately 2ms. The CONV bit
remains at a 1 from the time it is written until the conver-
sion is finished, at which time both CONV and BSY go
to 0. The CONV bit should be used when monitoring
the status of a user-initiated conversion.
Bits 4 and 3: Rate Select (RS2 and RS1).
These bits
control the frequency of the square-wave output when
the square wave has been enabled. The following table
shows the square-wave frequencies that can be select-
ed with the RS bits. These bits are both set to logic 1
(8.192kHz) when power is first applied.
Bit 2: Interrupt Control (INTCN).
This bit controls the
INT
/SQW signal. When the INTCN bit is set to logic 0, a
square wave is output on the
INT
/SQW pin. When the
INTCN bit is set to logic 1, a match between the time-
keeping registers and either of the alarm registers acti-
vates the
INT
/SQW (if the alarm is also enabled). The
corresponding alarm flag is always set regardless of
the state of the INTCN bit. The INTCN bit is set to logic
1 when power is first applied.
Bit 1: Alarm 2 Interrupt Enable (A2IE).
When set to
logic 1, this bit permits the alarm 2 flag (A2F) bit in the
status register to assert
INT
/SQW (when INTCN = 1).
When the A2IE bit is set to logic 0 or INTCN is set to
logic 0, the A2F bit does not initiate an interrupt signal.
The A2IE bit is disabled (logic 0) when power is first
applied.
Bit 0: Alarm 1 Interrupt Enable (A1IE).
When set to
logic 1, this bit permits the alarm 1 flag (A1F) bit in the
status register to assert
INT
/SQW (when INTCN = 1).
When the A1IE bit is set to logic 0 or INTCN is set to
logic 0, the A1F bit does not initiate the
INT
/SQW sig-
nal. The A1IE bit is disabled (logic 0) when power is
first applied.
DS3232
Extremely Accurate I
2
C RTC with
Integrated Crystal and SRAM
____________________________________________________________________
13
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
NAME:
EOSC
BBSQW
CONV
RS2
RS1
INTCN
A2IE
A1IE
POR*:
0
0
0
1
1
1
0
0
RS2
RS1
SQUARE-WAVE OUTPUT
FREQUENCY
0
0
1Hz
0
1
1.024kHz
1
0
4.096kHz
1
1
8.192kHz
SQUARE-WAVE OUTPUT FREQUENCY
Control Register (0Eh)
*
POR is defined as the first application of power to the device, either V
BAT
or V
CC
.
