DS3232
I
2
C Serial Data Bus
The DS3232 supports a bidirectional I
2
C bus and data
transmission protocol. A device that sends data onto the
bus is defined as a transmitter and a device receiving
data is defined as a receiver. The device that controls the
message is called a master. The devices that are con-
trolled by the master are slaves. The bus must be con-
trolled by a master device that generates the serial clock
(SCL), controls the bus access, and generates the START
and STOP conditions. The DS3232 operates as a slave
on the I
2
C bus. Connections to the bus are made through
the SCL input and open-drain SDA I/O lines. Within the
bus specifications, a standard mode (100kHz maximum
clock rate) and a fast mode (400kHz maximum clock rate)
are defined. The DS3232 works in both modes.
The following bus protocol has been defined (Figure 2):
• Data transfer may be initiated only when the bus is
not busy.
• During data transfer, the data line must remain stable
whenever the clock line is high. Changes in the data
line while the clock line is high are interpreted as
control signals.
Accordingly, the following bus conditions have been
defined:
Bus not busy:
Both data and clock lines remain
high.
Start data transfer:
A change in the state of the
data line from high to low, while the clock line is high,
defines a START condition.
Stop data transfer:
A change in the state of the data
line from low to high, while the clock line is high,
defines a STOP condition.
Data valid:
The state of the data line represents
valid data when, after a START condition, the data
line is stable for the duration of the high period of the
clock signal. The data on the line must be changed
during the low period of the clock signal. There is
one clock pulse per bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number
of data bytes transferred between the START and
the STOP conditions is not limited, and is determined
by the master device. The information is transferred
byte-wise and each receiver acknowledges with a
ninth bit.
Acknowledge:
Each receiving device, when
addressed, is obliged to generate an acknowledge
after the reception of each byte. The master device
must generate an extra clock pulse, which is associ-
ated with this acknowledge bit.
A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a
way that the SDA line is stable low during the high
period of the acknowledge-related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the
last byte that has been clocked out of the slave. In
this case, the slave must leave the data line high to
enable the master to generate the STOP condition.
Figures 3 and 4 detail how data transfer is accom-
plished on the I
2
C bus. Depending upon the state of
the R/
W
bit, two types of data transfer are possible:
Data transfer from a master transmitter to a slave
receiver.
The first byte transmitted by the master is
Extremely Accurate I
2
C RTC with
Integrated Crystal and SRAM
16
____________________________________________________________________
SDA
SCL
IDLE
1–7
8
9
1–7
8
9
1–7
8
9
START
CONDITION
STOP CONDITION
REPEATED START
SLAVE
ADDRESS
R/W
ACK
ACK
DATA
ACK/
NACK
DATA
MSB FIRST
MSB
LSB
MSB
LSB
REPEATED IF MORE BYTES
ARE TRANSFERRED
Figure 2. I
2
C Data Transfer Overview
