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DS3232

Power Control

This function is provided by a temperature-compensat-
ed voltage reference and a comparator circuit that
monitors the V

CC

level. When V

CC

is greater than V

PF

,

the part is powered by V

CC

. When V

CC

is less than V

PF

but greater than V

BAT

, the DS3232 is powered by V

CC

.

If V

CC

is less than V

PF

and is less than V

BAT

, the

device is powered by V

BAT

. See Table 1.

To preserve the battery, the first time V

BAT

is applied to

the device, the oscillator does not start up and no tem-
perature conversions take place until V

CC

exceeds V

PF

or until a valid I

2

C address is written to the part. After

the first time V

CC

is ramped up, the oscillator starts up

and the V

BAT

source powers the oscillator during

power-down and keeps the oscillator running. When
the DS3232 switches to V

BAT

, the oscillator may be dis-

abled by setting the 

EOSC

bit.

V

BAT

Operation

There are several modes of operation that affect the
amount of V

BAT

current that is drawn. While the device

is powered by V

BAT

and the serial interface is active,

active battery current, I

BATA

, is drawn. When the serial

interface is inactive, timekeeping current (I

BATT

), which

includes the averaged temperature conversion current,
I

BATTC

, is used (refer to Application Note 3644: 

Power

Considerations for Accurate Real-Time Clocks for
details). Temperature conversion current, I

BATTC

, is

specified since the system must be able to support the
periodic higher current pulse and still maintain a valid
voltage level. Data retention current, I

BATTDR

, is the

current drawn by the part when the oscillator is
stopped (

EOSC

= 1). This mode can be used to mini-

mize battery requirements for times when maintaining
time and date information is not necessary, e.g., while
the end system is waiting to be shipped to a customer.

Pushbutton Reset Function

The DS3232 provides for a pushbutton switch to be con-
nected to the 

RST

output pin. When the DS3232 is not in

a reset cycle, it continuously monitors the 

RST

signal for a

low going edge. If an edge transition is detected, the
DS3232 debounces the switch by pulling the 

RST

low.

After the internal timer has expired (PB

DB

), the DS3232

continues to monitor the 

RST

line. If the line is still low, the

DS3232 continuously monitors the line looking for a rising
edge. Upon detecting release, the DS3232 forces the

RST

pin low and holds it low for t

RST

.

The same pin, 

RST

, is used to indicate a power-fail con-

dition. When V

CC

is lower than V

PF

, an internal power-

fail signal is generated, which forces the 

RST

pin low.

When V

CC

returns to a level above V

PF

, the 

RST

pin is

held low for t

REC

to allow the power supply to stabilize.

If the oscillator is not running (see the 

Power Control

section) when V

CC

is applied, t

REC

is bypassed and

RST

immediately goes high.

Assertion of the 

RST

output, whether by pushbutton or

power-fail detection, does not affect the internal opera-
tion of the DS3232.

Real-Time Clock

With the clock source from the TCXO, the RTC provides
seconds, minutes, hours, day, date, month, and year
information. The date at the end of the month is automati-
cally adjusted for months with fewer than 31 days, includ-
ing corrections for leap year. The clock operates in either
the 24-hour or 12-hour format with an 

AM

/PM indicator.

The clock provides two programmable time-of-day
alarms and a programmable square-wave output. The

INT

/SQW pin either generates an interrupt due to alarm

condition or outputs a square-wave signal and the
selection is controlled by the bit INTCN.

SRAM

The DS3232 provides 236 bytes of general-purpose
battery-backed read/write memory. The I

2

C address

ranges from 14h to 0FFh. The SRAM can be written or
read whenever V

CC

or V

BAT

is greater than the mini-

mum operating voltage.

Address Map

Figure 1 shows the address map for the DS3232 time-
keeping registers. During a multibyte access, when the
address pointer reaches the end of the register space
(0FFh), it wraps around to location 00h. On an I

2

C

START or address pointer incrementing to location 00h,
the current time is transferred to a second set of regis-
ters. The time information is read from these secondary
registers, while the clock may continue to run. This
eliminates the need to reread the registers in case the
main registers update during a read.

I

2

C Interface

The I

2

C interface is accessible whenever either V

CC

or

V

BAT

is at a valid level. If a microcontroller connected to

the DS3232 resets because of a loss of V

CC

or other

Extremely Accurate I

2

C RTC with 

Integrated Crystal and SRAM

10

____________________________________________________________________

SUPPLY CONDITION

POWERED BY

V

CC

 < V

PF

, V

CC

 < V

BAT

V

BAT

V

CC

 < V

PF

, V

CC

 > V

BAT

V

CC

V

CC

 > V

PF

, V

CC

 < V

BAT

V

CC

V

CC

 > V

PF

, V

CC

 > V

BAT

V

CC

Table 1. Power Control

Summary of Contents for Maxim DS3232 Series

Page 1: ...atures Accuracy 2ppm from 0 C to 40 C Accuracy 3 5ppm from 40 C to 85 C Battery Backup Input for Continuous Timekeeping Operating Temperature Ranges Commercial 0 C to 70 C Industrial 40 C to 85 C 236...

Page 2: ...ard Layout and Assembly section PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VCC 2 3 3 3 5 5 Supply Voltage VBAT 2 3 3 0 5 5 V Logic 1 Input SDA SCL VIH 0 7 x VCC VCC 0 3 V Logic 0 Input SDA SCL VIL...

Page 3: ...63 31 69 0 C to 40 C 2 2 Frequency Stability vs Temperature f fOUT VCC 3 3V or VBAT 3 3V 40 C to 0 C and 40 C to 85 C 3 5 3 5 ppm Frequency Stability vs Voltage f V VCC 3 3V or VBAT 3 3V 1 ppm V 40 C...

Page 4: ...de 100 Data Setup Time Note 10 tSU DAT Standard mode 250 ns Fast mode 0 6 Start Setup Time tSU STA Standard mode 4 7 s Fast mode 300 Rise Time of Both SDA and SCL Signals Note 11 tR Standard mode 20 0...

Page 5: ...te I2C RTC with Integrated Crystal and SRAM _____________________________________________________________________ 5 Pushbutton Reset Timing tRST PBDB RST Power Switch Timing VCC VPF MAX RST VPF MIN tV...

Page 6: ...of the falling edge of SCL Note 9 The maximum tHD DAT needs only to be met if the device does not stretch the low period tLOW of the SCL signal Note 10 A fast mode device can be used in a standard mod...

Page 7: ...DS3232 toc03 TEMPERATURE C SUPPLY CURRENT A 80 60 40 20 0 20 0 700 0 800 0 900 0 600 40 VCC 0V BB32kHz 0 VBAT 3 4V VBAT 3 0V FREQUENCY DEVIATION vs TEMPERATURE vs AGING DS3232 toc04 TEMPERATURE C FREQ...

Page 8: ...and accurate reference clock and maintains the RTC to within 2 minutes per year accu racy from 40 C to 85 C The TCXO frequency output is available at the 32kHz pin The RTC is a low power clock calend...

Page 9: ...t When using the device with the VBAT input as the primary power source this pin should be decoupled using a 0 1 F to 1 0 F low leakage capacitor When using the device with the VBAT input as the backu...

Page 10: ...ising edge Upon detecting release the DS3232 forces the RST pin low and holds it low for tRST The same pin RST is used to indicate a power fail con dition When VCC is lower than VPF an internal power...

Page 11: ...RAM ____________________________________________________________________ 11 Figure 1 Address Map for DS3232 Timekeeping Registers and SRAM Note Unless otherwise specified the registers state is not de...

Page 12: ...ch of the time of day date alarm registers are mask bits Table 2 When all the mask bits for each alarm are logic 0 an alarm only occurs when the values in the timekeeping registers match the correspon...

Page 13: ...e bits control the frequency of the square wave output when the square wave has been enabled The following table shows the square wave frequencies that can be select ed with the RS bits These bits are...

Page 14: ...Output EN32kHz This bit indi cates the status of the 32kHz pin When set to logic 1 the 32kHz pin is enabled and outputs a 32 768kHz square wave signal When set to logic 0 the 32kHz pin goes low The in...

Page 15: ...s section for a graph showing the effect of the register on accu racy over temperature Temperature Registers 11h 12h Temperature is represented as a 10 bit code with a res olution of 0 25 C and is acc...

Page 16: ...clock signal The data on the line must be changed during the low period of the clock signal There is one clock pulse per bit of data Each data transfer is initiated with a START condition and terminat...

Page 17: ...___________________________________________________ 17 A XXXXXXXX A 1101000 S 0 XXXXXXXX A XXXXXXXX A XXXXXXXX A P R W WORD ADDRESS n DATA n DATA n 1 DATA n X S START A ACKNOWLEDGE ACK P STOP R W READ...

Page 18: ...are after reception of the slave address and direction bit The slave address byte is the first byte received after the master generates a START condition The slave address byte contains the 7 bit DS32...

Page 19: ...ower is applied and the oscillator is disabled 9 Added a paragraph to the Pushbutton Reset Function section about how the RST output operation does not affect the device s internal operation 10 3 10 0...

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