Detection and Action Upon
New Device Connection
When a new device is connected to the system, the
device must be authenticated and the device’s KSV
checked against the revocation list. The downstream
µCs can set the NEW_DEV_CONN bit of the upstream
receiver and invoke an interrupt to notify upstream µ
Cs.
Notification of Start of Authentication and
Enable of Encryption to Downstream Links
HDCP repeaters do not immediately begin authentication
upon startup or detection of a new device, but instead wait
for an authentication request from the upstream transmit
-
ter/repeaters.
Use the following procedure to notify downstream links of
the start of a new authentication request:
● 1) Host µC begins authentication with the HDCP
repeater’s input receiver.
● 2) When AKSV is written to HDCP repeater’s input
receiver, its AUTH_STARTED bit is automatically set
and its GPIO1 goes high (if GPIO1_FUNCTION is
set to high).
● 3) HDCP repeater’s µC waits for a low-to-high tran
-
sition on HDCP repeater input receiver’s AUTH_
STARTED bit and/or GPIO1 (if configured) and starts
authentication downstream.
● 4) HDCP repeater’s µC resets the AUTH_STARTED
bit.
Set GPIO0_FUNCTION to high to have GPIO0 follow the
ENCRYPTION_ENABLE bit of the receiver. The repeater
µC can use this function for notification when encryption
is enabled/disabled by
an upstream µC.
Applications Information
Self PRBS Test
The serializers include a PRBS pattern generator which
works with bit-error verification in the deserializer. To run
the PRBS test, first disable HDCP encryption. Next, set
DISHSFILT, DISVSFILT and DISDEFILT to ‘1’, to disable
glitch filter in the deserializer. Then, set PRBSEN = 1
(0x04, D5) in the serializer and then in the deserializer.
To exit the PRBS test, set PRBSEN = 0 (0x04, D5) in the
deserializer and then in the serializer.
Dual µC Control
Usually systems have one microcontroller to run the
control channel, located on the serializer side for display
applications or on the deserializer side for image-sensing
applications. However, a µC can reside on each side
simultaneously, and trade off running the control channel.
In this case, each µC can communicate with the serializer
and deserializer and any peripheral devices.
Contention will occur if both µCs attempt to use the
control channel at the same time. It is up to the user to
prevent this contention by implementing a higher level
protocol. In addition, the control channel does not provide
arbitration between I
2
C masters on both sides of the link.
An acknowledge frame is not generated when communi
-
cation fails due to contention. If communication across the
serial link is not required, the µCs can disable the forward
and reverse control channel using the FWDCCEN and
REVCCEN bits (0x04, D[1:0]) in the serializer/deserial
-
izer. Communication across the serial link is stopped and
contention between µCs cannot occur.
As an example of dual µC use in an image-sensing appli
-
cation, the serializer can be in sleep mode and waiting
for wake-up by µC on the deserializer side. After wake-
up, the serializer-side µC assumes master control of the
serializer’s
registers.
Jitter-Filtering PLL
In some applications, the clock input (RXCLKIN) includes
noise, which reduces link reliability. The clock input has a
programmable narrowband jitter-filter PLL that attenuates
frequencies higher than 100kHz (typical). Enable the jit
-
ter-filter by setting DISJITFILT = 0 (0x05, D6).
RXCLKIN Spread Tracking
The serializers can operate with a spread RXCLKIN sig
-
nal. When using a spread RXCLKIN, disable the jitter-filter
by setting DISJITFILT = 1 (0x05, D6) and set X7PLLHIBW
=1 (0x0C, D7). Do not exceed 0.5% spread for f
RXCLKIN
> 50MHz, and 1% spread for f
RXCLKIN
< 50MHz, and
keep modulation less than 40kHz. In addition, turn off
spread spectrum in the serializer and deserializer. The
serializer and
deserializer track the spread on RXCLKIN.
Changing the Clock Frequency
It is recommend
ed that the serial link be enabled after
the video clock (f
RXCLKIN_
) and the control-channel
clock (f
UART
/f
µC
) are stable. When changing the clock
frequency, stop the video clock for 5µs, apply the clock
at the new frequency, then restart the serial link or toggle
SEREN. On-the-fly changes in clock frequency are possi
-
ble if the new frequency is immediately stable and without
glitches. The reverse control channel remains unavailable
for 500µs after serial link start or stop. When using the
UART interface, limit on-the-fly changes in f
UART
to fac
-
tors of less than 3.5 at a time to ensure that the device
recognizes the UART sync pattern. For example, when
lowering the UART frequency from 1Mbps to 100kbps,
first send data at 333kbps then at 100kbps for reduction
ratios of 3 and 3.333, respectively.
MAX9277/MAX9281
3.12Gbps GMSL Serializers for Coax or
STP Output Drive and LVDS Input
www.maximintegrated.com
Maxim Integrated │
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