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Maxim Integrated MAX9277, Manual

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Maxim Integrated MAX9277 Manual Download Page 34

Control Channel and Register Programming

The control channel is available for the µC to send and 

receive  control  data  over  the  serial  link  simultaneously 

with the high-speed data. The µC controls the link from 

either the serializer or the deserializer side to support 

video-display or image-sensing applications. The control 

channel  between  the  µC  and  serializer  or  deserializer 

runs  in  base  mode  or  bypass  mode  according  to  the 

mode selection (MS) input of the device connected to the 

µC. Base mode is a half-duplex control channel and the 

bypass  mode  is  a  full-duplex  control  channel.  The  total 

maximum forward or reverse control channel delay is 2

F

s 

(UART) or 2 bit times (I

2

C) from the input of one device 

to the output of the other. I

2

C delay is measured from a 

START condition to START condition.

UART Interface

In  base  mode,  the  µC  is  the  host  and  can  access  the 

registers of both the serializer and deserializer from either 

side of the link using the GMSL UART protocol. The µC 

can also program the peripherals on the remote side by 

sending the UART packets to the serializer or deserializer, 

with  the  UART  packets  converted  to  I

2

C  by  the  device 

on  the  remote  side  of  the  link.  The  µC  communicates 

with a UART peripheral in base mode (through INTTYPE 

register  settings),  using  the  half-duplex  default  GMSL 

UART  protocol  of  the  serializer/deserializer.  The  device 

addresses of the serializer and deserializer in base mode 

are programmable.

When the peripheral interface is I

2

C, the serializer/dese-

rializer  converts  UART  packets  to  I

2

C  that  have  device 

addresses different from those of the serializer or dese-

rializer.  The  converted  I

2

C bit rate is the same as the 

original UART bit rate.

The  deserializer  uses  differential  line  coding  to  send 

signals over the reverse channel to the serializer. The bit 

rate  of  the  control  channel  is  9.6kbps  to  1Mbps  in  both 

directions.  The  serializer  and  deserializer  automatically 

detect the control-channel bit rate in base mode. Packet 

bit rate changes can be made in steps of up to 3.5 times 

higher or lower than the previous bit rate. See “Changing 

the Clock Frequency” for more information.

Figure 25

 shows the UART protocol for writing and read

-

ing in base mode between the 

µ

C and the serializer/

deserializer.

Figure  26

  shows  the  UART  data  format  (even  parity  is 

used). 

Figure 27

 and 

Figure 28

 detail the formats of the 

SYNC byte (0x79) and the ACK byte (0xC3). The µC

 and 

the  connected  slave  chip  generate  the  SYNC  byte  and 

ACK byte, respectively. Events such as device wake-up 

and GPI generate transitions on the control channel that 

can be ignored by the µC

. Data written to the serializer 

registers  do  not  take  effect  until  after  the  acknowledge 

byte is sent. This allows the 

µC to verify that write com

-

mands are received without error, even if the result of the 

write command directly affects the serial link. The slave 

uses the SYNC byte to synchronize with the host UART’s 

data  rate.  If  the  GPI  or  MS  inputs  of  the  deserializer 

toggle  while  there  is  control-channel  communication,  or 

if a line fault occurs, the control-channel communication 

will  be  corrupted.  In  the  event  of  a  missed  or  delayed 

acknowledge  (~1ms  due  to  control  channel  timeout), 

the 

µC should assume there was an error in the packet 

transmission or response. In base mode, the 

µC

 must 

keep  the  UART  Tx/Rx  lines  high  no  more  than  four  bit 

times between bytes in a packet. Keep the UART Tx/Rx 

lines high for at least 16 bit-times before starting to send 

a new packet.

Figure 25. GMSL UART Protocol for Base Mode

WRITE DATA FORMAT

SYNC

REG ADDR NUMBER OF BYTES

SYNC

DEV ADDR + R/W REG ADDR NUMBER OF BYTES

BYTE 1

BYTE N

ACK

BYTE N

BYTE 1

ACK

MASTER READS FROM SLAVE

READ DATA FORMAT

MASTER WRITES TO SLAVE

MASTER WRITES TO SLAVE

MASTER READS FROM SLAVE

DEV ADDR + R/W

MAX9277/MAX9281

3.12Gbps GMSL Serializers for Coax or  

STP Output Drive and LVDS Input

www.maximintegrated.com

Maxim Integrated  │

 

34

Summary of Contents for MAX9277

Page 1: ...d free 48 pin 7mm x 7mm TQFN with exposed pad and 0 5mm lead pitch Applications High Resolution Automotive Navigation Rear Seat Infotainment Megapixel Camera Systems Features and Benefits Ideal for High Definition Video Applications Drives Low Cost 50Ω Coax Cable and FAKRA Connectors or 100Ω STP 104MHz High Bandwidth Mode Supports 1920x720p 60Hz Display With 24 Bit Color Serializer Pre Deemphasis ...

Page 2: ...ram 20 Detailed Description 26 Register Mapping 26 Input Bit Map 27 Serial Link Signaling and Data Format 29 Reserved Bit RES CNTL1 30 Data Rate Selection 30 High Bandwidth Mode 30 Audio Channel 30 Audio Channel Input 32 Reverse Control Channel 33 Control Channel and Register Programming 34 UART Interface 34 Interfacing Command Byte Only I2C Devices With UART 35 UART Bypass Mode 35 I2C Interface 3...

Page 3: ...CP 48 Encryption Enable 48 Synchronization of Encryption 48 Repeater Support 48 HDCP Authentication Procedures 49 HDCP Protocol Summary 49 Example Repeater Network Two µCs 53 Detection and Action Upon New Device Connection 57 Notification of Start of Authentication and Enable of Encryption to Downstream Links 57 Applications Information 57 Self PRBS Test 57 Dual µC Control 57 Jitter Filtering PLL ...

Page 4: ...ine Fault Detection 59 Internal Input Pulldowns 59 Choosing I2C UART Pullup Resistors 59 AC Coupling 60 Selection of AC Coupling Capacitors 60 Power Supply Circuits and Bypassing 60 Power Supply Table 60 Cables and Connectors 61 Board Layout 61 ESD Protection 61 Typical Application Circuit 71 Ordering Information 71 Chip Information 71 Package Information 71 Revision History 72 ...

Page 5: ...S Timing Parameters 25 Figure 15 LVDS Input Timing 28 Figure 16 LVDS Clock and Bit Assignment 28 Figure 17 3 Channel Mode Serial Data Format 29 Figure 18 4 Channel Mode Serial Data Format 29 Figure 19 High Bandwidth Mode Serial Data Format 30 Figure 21 8 Channel TDM 24 Bit Samples Padded with Zeros 32 Figure 22 6 Channel TDM 24 Bit Samples No Padding 32 Figure 20 Audio Channel Input Format 32 Figu...

Page 6: ...e to Multiple Registers 39 Figure 37 Format for I2C Read 39 Figure 38 2 1 Coax Splitter Connection Diagram 43 Figure 39 Coax Connection Diagram 43 Figure 40 State Diagram CDS LOW Video Display Application 46 Figure 41 State Diagram CDS HIGH Image Sensing Application 47 Figure 42 Example Network with One Repeater and Two µCs Tx GMSL Serializers Rx Deserializers 53 Figure 43 Human Body Model ESD Tes...

Page 7: ...le 14 Startup Procedure for Image Sensing Applications 46 Table 15 Startup HDCP Authentication and Normal Operation Deserializer is not a Repeater First Part of the HDCP Authentication Protocol 49 Table 16 Link Integrity Check Normal Performed Every 128 Frames After Encryption is Enabled 51 Table 17 Optional Enhanced Link Integrity Check Performed Every 16 Frames After Encryption is Enabled 52 Tab...

Page 8: ...ge VIL1 0 35 x VIOVDD V Input Current IIN1 VIN 0V to VIOVDD 10 20 µA THREE LEVEL LOGIC INPUTS CONF0 CONF1 ADD0 ADD1 BWS High Level Input Voltage VIH 0 7 x VIOVDD V Low Level Input Voltage VIL 0 3 x VIOVDD V Mid Level Input Current IINM Note 4 10 10 µA Input Current IIN 150 150 µA SINGLE ENDED OUTPUT GPO High Level Output Voltage VOH1 IOUT 2mA VIOVDD 0 2 V Low Level Output Voltage VOL1 IOUT 2mA 0 2...

Page 9: ...hasis setting Figure 2 240 425 Change in VOD Between Complementary Output States ΔVOD Preemphasis off deemphasis only 15 mV Output Offset Voltage VOUT VOUT 2 VOS VOS Preemphasis off 1 1 1 4 1 56 V Change in VOS between Complementary Output States ΔVOS 15 mV Output Short Circuit Current IOS VOUT or VOUT 0V 62 mA VOUT or VOUT 1 9V 25 Magnitude of Differential Output Short Circuit Current IOSD VOD 0V...

Page 10: ...Figure 4 2 47 V LVDS INPUTS RXIN_ RXCLKIN_ Differential Input High Threshold VTH VCM 1 2V 50 mV Differential Input Low Threshold VTL VCM 1 2V 50 mV Input Differential Termination Resistance RTERM 85 110 135 Ω Input Current IIN IIN PWDN high or low IN and IN are shorted 25 25 µA Power Off Input Current IIN0 IIN0 VAVDD VDVDD VIOVDD 0V 40 40 µA POWER SUPPLY Total Supply Current AVDD DVDD IOVDD Note 6...

Page 11: ...e 6 VESD Human body model RD 1 5kΩ CS 100pF 8 kV IEC 61000 4 2 RD 330Ω CS 150pF Contact discharge 10 Air discharge 12 ISO 10605 RD 2kΩ CS 330pF Contact discharge 10 Air discharge 25 RXIN_ RXCLKIN_ Note 7 VESD Human body model RD 1 5kΩ CS 100pF 8 kV IEC 61000 4 2 RD 330Ω CS 150pF Contact discharge 6 Air discharge 20 ISO 10605 RD 2kΩ CS 330pF Contact discharge 8 Air discharge 30 All Other Pins Note ...

Page 12: ...111 I2CSLVSH 00 400 1000 kHz START Condition Hold Time tHD STA fSCL range Low 4 0 µs Mid 0 6 High 0 26 Low Period of SCL Clock tLOW fSCL range Low 4 7 µs Mid 1 3 High VIOVDD 1 7V to 3V Note 9 0 6 VIOVDD 3 0V to 3 6V 0 5 High Period of SCL Clock tHIGH fSCL range Low 4 0 µs Mid 0 6 High 0 26 Repeated START Condition Setup Time tSU STA fSCL range Low 4 7 µs Mid 0 6 High 0 26 Data Hold Time tHD DAT fS...

Page 13: ...ial Output Rise Fall Time tR tF 20 to 80 VOD 400mV RL 100Ω serial bit rate 3 12Gbps 90 150 ps Total Serial Output Jitter Differential Output tTSOJ1 3 12Gbps PRBS signal measured at VOD 0V differential preemphasis disabled Figure 7 0 21 UI Deterministic Serial Output Jitter Differential Output tDSOJ2 3 12Gbps PRBS signal measured at VOD 0V differential preemphasis disabled Figure 7 0 09 UI Total Se...

Page 14: ...e I2C bus standard tVD ACK max 0 45µs Note 12 Not production tested Guaranteed by design Note 13 Measured in serial link bit times Bit time 1 30 x fPCLKIN for BWS 0 or open Bit time 1 40 x fPCLKIN for BWS 1 Note 14 I2C valid times apply only when the device is operating as a local side device PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS GPI to GPO Delay tGPIO Deserializer GPI to serializer GPO Fi...

Page 15: ... 160 170 180 5 20 35 50 65 80 SUPPLY CURRENT mA RXCLKIN FREQUENCY MHz SUPPLY CURRENT vs RXCLKIN FREQUENCY BWS HIGH toc03 PRBS ON COAX MODE SS OFF HDCP OFF PREEMPHASIS 0x00 PREEMPHASIS 0x01 to 0x04 PREEMPHASIS 0x0B to 0x0F 120 130 140 150 160 170 180 5 15 25 35 45 55 65 75 85 95 105 SUPPLY CURRENT mA RXCLKIN FREQUENCY MHz SUPPLY CURRENT vs RXCLKIN FREQUENCY BWS LOW toc04 PRBS ON COAX MODE PE OFF HD...

Page 16: ...AD 4 SPREAD fPCLKIN 33 3MHz 100 90 80 70 60 50 40 30 20 10 0 10 62 63 64 65 66 67 68 69 70 71 OUTPUT POWER dBm RXCLKIN FREQUENCY MHz OUTPUT SPECTURM vs RXCLKIN FREQUENCY VARIOUS SPREAD toc08 2 SPREAD 0 SPREAD 1 SPREAD 0 5 SPREAD 4 SPREAD fPCLKIN 66 6MHz 0 20 40 60 80 100 120 0 5 10 15 20 25 RXCLKIN FREQUENCY MHz CABLE LENGTH m MAXIMUM RXCLKIN FREQUENCY vs COAX CABLE LENGTH BER 10 10 toc09 BER CAN ...

Page 17: ...D 16 SD I2S TDM Serial Data Input with Internal Pulldown to GND Disable I2S TDM encoding to use SD as an additional control data input latched on the selected edge of PCLKIN Encrypted when HDCP is enabled 17 SCK I2S TDM Serial Clock Input with Internal Pulldown to GND TOP VIEW MAX9277 MAX9281 TQFN 7mm x 7mm x 0 75mm 13 14 15 16 17 18 19 20 21 22 23 24 AGND LVDSVDD AVDD SD SCK WS CNTL1 CNTL2 AGND D...

Page 18: ...of the serializer s I2C Master Slave 26 TX SCL UART Transmit I2C Serial Clock Input Output with Internal 30kΩ Pullup to IOVDD Function is determined by the state of CONF 1 0 at power up Table 10 TX SCL has an open drain driver and requires a pullup resistor TX Output of the serializer s UART SCL Clock input output of the serializer s I2C Master Slave 27 CONF1 Three Level Configuration Input The st...

Page 19: ...3 1 Used only in high bandwidth mode BWS open CNTL3 not encrypted when HDCP is enabled MAX9281 only 44 MS CNTL0 Mode Select Auxiliary Control Signal Input with Internal Pulldown to GND Function is determined by the MSCNTL0 register bit and defaults to MS on power up MS MSCNTL0 0 Set MS low to select base mode Set MS high to select the bypass mode CNTL0 MSCNTL0 1 Used only in high bandwidth mode BW...

Page 20: ...CB CNTL 3 0 9b10b DIN 28 27 30 BIT FCC HDCP CONTROL AUDIO FIFO 7x PLL CONTROL 9b10b SYNC VIDEO CLKDIV SSPLL RES CNTL1 4 CH CNTL0 MS CNTL3 CDS CNTL2 CNTL1 RXIN3 4CH RXIN2 RXIN1 RXIN0 RXCLKIN RGB 23 18 4 CH OR 9b10b RGB 17 0 CML TX LMN1 LMN0 LFLT OUT CX TP OUT RX PWDN FILTER PLL LINE FAULT DETECT CNTL2 4 CH CNTL2 9b10b CNTL0 CNTL3 9b10b MS CDS MAX9277 MAX9281 3 12Gbps GMSL Serializers for Coax or ST...

Page 21: ... OUT VOD VOS GND RL 2 RL 2 OUT OUT OUT OUT OUT VOS VOS OUT OUT 2 VOS VOD VOD VOD 0V DVOS VOS VOS DVOD VOD VOD VOD OUT OUT VOS VOD P VOD D SERIAL BIT TIME OUT OR OUT VO 2 VO 2 VO VO MAX9277 MAX9281 3 12Gbps GMSL Serializers for Coax or STP Output Drive and LVDS Input www maximintegrated com Maxim Integrated 21 ...

Page 22: ...UT LOGIC OUT GMSL SERIALIZER GMSL SERIALIZER 45 3kΩ LMN1 LMN1 LMN0 LMN0 45 3kΩ 1 8V 4 99kΩ 49 9kΩ 49 9kΩ 4 99kΩ TWISTED PAIR COAX OUT OUT CONNECTORS GMSL SERIALIZER 45 3kΩ LMN0 49 9Ω 1 8V 4 99kΩ 49 9kΩ OUT OUT RXCLKIN RXCLKIN RXIN0 TO RXIN3 RXIN0 TO RXIN3 CNTL_ MAX9277 MAX9281 3 12Gbps GMSL Serializers for Coax or STP Output Drive and LVDS Input www maximintegrated com Maxim Integrated 22 ...

Page 23: ...EDGE A STOP CONDITION P VIOVDD x 0 7 VIOVDD x 0 3 VIOVDD x 0 7 VIOVDD x 0 3 tSU STA tLOW tHIGH tBUF tHD STA tr tSP tf tSU DAT tHD DAT tVD DAT tVD ACK tSU STO 1 fSCL 800mVP P tTSOJ1 2 tTSOJ1 2 RXIN_ RXIN_ RXCLKIN CNTL_ RXCLKIN tSET tHOLD VIHMIN VILMAX MAX9277 MAX9281 3 12Gbps GMSL Serializers for Coax or STP Output Drive and LVDS Input www maximintegrated com Maxim Integrated 23 ...

Page 24: ...TIVE CHANNEL DISABLED REVERSE CONTROL CHANNEL ENABLED REVERSE CONTROL CHANNEL ENABLED PWDN MUST BE HIGH RXCLKIN tLOCK 500µs tGPIO tGPIO VOH_MIN VOL_MAX VIH_MIN VIL_MAX DESERIALIZER GPI SERIALIZER GPO N 1 N FIRST BIT LAST BIT N N 1 N 1 N 2 N 3 RXCLKIN RXCLKIN OUT OUT RXIN_ RXIN_ EXPANDED TIME SCALE tSD MAX9277 MAX9281 3 12Gbps GMSL Serializers for Coax or STP Output Drive and LVDS Input www maximin...

Page 25: ...VE tPU VIH1 REVERSE CONTROL CHANNEL DISABLED REVERSE CONTROL CHANNEL ENABLED REVERSE CONTROL CHANNEL DISABLED REVERSE CONTROL CHANNEL ENABLED PWDN RXCLKIN RXCLKIN WS tHOLD tSET tHOLD tSET tHC tSCK tLC SCK SD CNTL0 MAX9277 MAX9281 3 12Gbps GMSL Serializers for Coax or STP Output Drive and LVDS Input www maximintegrated com Maxim Integrated 25 ...

Page 26: ...tion are availa ble Base mode uses either I2C or GMSL UART protocol while bypass mode uses a user defined UART protocol UART protocol allows full duplex communication while I2C allows half duplex communication Spread spectrum is available to reduce EMI on the serial output The serial output and LVDS input complies with ISO 10605 and IEC 61000 4 2 ESD protection standards Register Mapping Registers...

Page 27: ...NPUT PIN BIT POSITION R 5 0 DIN 5 0 Used Used Used G 5 0 DIN 11 6 Used Used Used B 5 0 DIN 17 12 Used Used Used HS VS DE DIN18 HS DIN19 VS DIN20 DE Used Used Used R 7 6 DIN 22 21 Not used Used Used G 7 6 DIN 24 23 Not used Used Used B 7 6 DIN 26 25 Not used Used Used RES CNTL 2 1 RES CNTL 2 1 Not used Used Used CNTL3 CNTL0 CDS CNTL3 MS CNTL0 Not used Used Not used I2S TDM WS SCK SD Used Used Used ...

Page 28: ...XIN0 RXIN0 RXCLKIN RXIN1 RXIN1 RXIN2 RXIN2 RXIN3 RXIN3 RXCLKIN CNTL1 CNTL2 SD SD CNTL0 CNTL3 CNTL0 CNTL3 CNTL1 DIN27 CNTL2 DIN28 CNTL0 CNTL3 ONLY USED IN HIGH BANDWIDTH MODES RXIN3 CNTL1 CNTL2 ONLY USED IN 32 BIT AND HIGH BANDWIDTH MODES R1 CYCLE N 1 CYCLE N RXIN0 RXIN0 RXCLKIN RXCLKIN RXIN1 RXIN1 RXIN2 RXIN2 R0 G0 R5 R4 R3 R2 R1 R0 G2 G1 B1 B0 G5 G4 G3 G2 G1 B3 B2 DE VS HS B5 B4 B3 B2 RXIN3 RXIN3...

Page 29: ...nel Mode Serial Data Format 24 BITS PACKET PARITY CHECK BIT ACB FCC PCB D0 D1 R0 R1 B5 HS VS DE D20 D19 D18 D17 MAX9281 NOTE VS HS MUST BE SET AT DIN 19 18 FOR HDCP FUNCTIONALITY ONLY DIN 17 0 AND ACB HAVE HDCP ENCRYPTION RGB DATA CONTROL BITS DIN0 DIN1 DIN17 DIN18 HS DIN19 VS DIN20 DE SERIAL DATA INPUT PIN INPUT SIGNAL WS SCK SD RX SDA TX SCL AUDIO ENCODE I2S TDM AUDIO UART I2C FORWARD CONTROL CH...

Page 30: ... to be syn chronized with RXCLKIN_ The serializer automatically encodes audio data into a single bit stream synchronous with RXCLKIN_ The deserializer decodes the audio stream and stores audio words in a FIFO Audio rate detection uses an internal oscillator to continuously determine the audio data rate and output the audio in I2S format The audio channel is enabled by default When the audio channe...

Page 31: ... 92 8 111 8 139 7 167 6 6 8 152 2 182 7 16 88 6 106 3 117 7 141 8 177 2 18 80 2 93 3 106 6 128 4 160 5 20 73 3 88 0 97 3 117 3 146 6 175 9 24 62 5 75 0 83 0 100 125 150 175 32 48 3 57 9 64 1 77 2 96 5 115 9 135 2 154 5 173 8 8 8 123 7 148 4 164 3 16 69 9 83 8 92 8 111 8 139 7 167 6 18 62 5 75 0 83 0 100 0 125 0 150 0 175 0 20 57 1 68 5 75 8 91 3 114 2 137 0 159 9 182 7 24 48 3 57 9 64 1 77 2 96 5 ...

Page 32: ... does not affect operation of the audio channel The polarity for WS and SCK edges is programmable The following are examples of acceptable input formats Figure 21 8 Channel TDM 24 Bit Samples Padded with Zeros Figure 22 6 Channel TDM 24 Bit Samples No Padding Figure 20 Audio Channel Input Format WS SCK SD 256 SCK CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 MSB 24 BIT DATA LSB 8 BITS ZERO 32 SCK WS SCK SD SCK ...

Page 33: ... channel The reverse control channel is available 2ms after power up The serializer temporarily disables the reverse control channel for 500µs after starting stop ping the forward serial link Figure 23 Stereo I2S 24 Bit Samples Padded with Zeros Figure 24 Stereo I2S 16 Bit Samples No Padding 32 SCK WS SCK SD 64 SCK LEFT CHANNEL MSB 24 BIT DATA LSB 8 BITS ZERO RIGHT CHANNEL WS SCK SD 32 SCK LEFT CH...

Page 34: ...1Mbps in both directions The serializer and deserializer automatically detect the control channel bit rate in base mode Packet bit rate changes can be made in steps of up to 3 5 times higher or lower than the previous bit rate See Changing the Clock Frequency for more information Figure 25 shows the UART protocol for writing and read ing in base mode between the µC and the serializer deserializer ...

Page 35: ...s sampling of the UART signal by RXCLKIN_ Set MS high in the serializer to put the control channel into bypass mode For applications with the FC connected to the deserializer set the MS pin on the deserializer There is a 1ms wait time between switching MS high and the bypass control channel being active do not send a UART command during this time There is no delay time when switching to bypass mod...

Page 36: ...1 1 1 1 7 1 1 8 1 1 1 7 DEV ID R A A A P DATA 0 DATA N SLAVE TO MASTER S START P STOP A ACKNOWLEDGE 11 SYNC FRAME REGISTER ADDRESS NUMBER OF BYTES DEVICE ID WR DATA 0 DEV ID A 11 11 11 11 DATA N 11 11 S 1 1 1 ACK FRAME 7 MASTER TO SLAVE 8 SERIALIZER DESERIALIZER PERIPHERAL W 1 REG ADDR 8 A 1 1 8 1 11 SYNC FRAME REGISTER ADDRESS NUMBER OF BYTES DEVICE ID RD 11 11 11 11 ACK FRAME DATA 0 11 DATA N 11...

Page 37: ...on con sists of a START condition Figure 6 sent by a master followed by the device s 7 bit slave address plus a R W bit a register address byte one or more data bytes and finally a STOP condition START and STOP Conditions Both SCL and SDA remain high when the interface is not busy A master signals the beginning of a transmission with a START S condition by transitioning SDA from high to low while ...

Page 38: ...device resets the bus with the I2C START condition for reads When the R W bit is set to 1 the serializers transmit data to the master thus the master is reading from the device Format for Writing Writes to the serializers comprise the transmission of the slave address with the R W bit set to zero followed by at least one byte of information The first byte of information is the register address or ...

Page 39: ...e Figure 36 Format for Write to Multiple Registers Figure 37 Format for I2C Read S 1 0 0 0 ADDRESS 0x80 0 WRITE 0 0 0 0 A 0 0 0 0 REGISTER ADDRESS 0x00 0 0 0 0 A P D7 D6 D5 D4 REGISTER 0x00 WRITE DATA D3 D2 D1 D0 A S START BIT P STOP BIT A ACK D_ DATA BIT S START BIT P STOP BIT A ACK N NACK D_ DATA BIT S 1 0 0 0 ADDRESS 0x80 0 WRITE 0 0 0 0 A 0 0 0 0 REGISTER ADDRESS 0x00 0 0 0 0 A D7 D6 D5 D4 REG...

Page 40: ... stores the GPI input state GPO is low after power up The µC can set GPO by writing to the SETGPO register bit Do not send a logic low value on the deserializer RX SDA input UART mode longer than 100µs in either base or bypass mode to ensure proper GPO GPI functionality GPO GPI commands will override and corrupt an I2C UART command in progress Pre Deemphasis Driver The serial line driver employs c...

Page 41: ...4 6 500 200 10 5 1110 13 7 500 150 14 0 1111 12 8 500 100 SS SPREAD 000 No spread spectrum Power up default depends on CONF 1 0 001 0 5 spread spectrum Power up default depends on CONF 1 0 010 1 5 spread spectrum 011 2 spread spectrum 100 No spread spectrum 101 1 spread spectrum 110 3 spread spectrum 111 4 spread spectrum 3 CHANNEL OR HIGH BANDWIDTH MODE RXCLKIN FREQUENCY MHz 4 CHANNEL MODE RXCLKI...

Page 42: ... peripherals Assign a unique address to send control data to one deserializer Leave all unused IN_ pins unconnected or connect them to ground through 50Ω and a capacitor for increased power supply rejection If OUT is not used connect OUT to VDD through a 50Ω resistor Figure 39 When there are µCs at the serializer and at each deserializer only one µC can communicate at a time Disable forward and re...

Page 43: ...serializer and register 0x11 in the deserializer in both devices to use a 1Mbps bit rate Certain limitations apply when using the fast high immunity mode Table 12 Figure 38 2 1 Coax Splitter Connection Diagram Figure 39 Coax Connection Diagram Table 10 CONF 1 0 Input Map CONF1 CONF0 CONTROL CHANNEL MODE I2CSEL SPREAD ENABLE SSEN DATA RATE SELECT DRS Low Low UART 0 Disabled 0 High rate 0 Low High U...

Page 44: ...wn Mode The serializers have a power down mode which fur ther reduces power consumption compared to Sleep Mode Set PWDN low to enter power down mode In power down the serial outputs remain high impedance Entering power down resets the device s registers Upon exiting power down the state of external pins CONF 1 0 ADD 2 0 CX TP GPO HIM and BWS are latched Configuration Link The control channel can o...

Page 45: ...the other always connects that configuration input low 1 Powers up Powers up and loads default settings Establishes video link when valid RXCLK available Powers up and loads default settings Powers up and loads default settings Locks to video link signal if available 2 Enables serial link by setting SEREN 1 or configuration link by setting SEREN 0 and CLINKEN 1 if valid RXCLK not available and get...

Page 46: ...tings 3 Wakes up the serializer by sending dummy packet and then writing SLEEP 0 within 8 ms May not get an acknowledge or gets a dummy acknowledge if not locked Wakes up LOW HIGH 1 0 SEREN POWER UP VALUE SEREN 0 FOR 8ms VIDEO LINK OPERATING VIDEO LINK PRBS TEST WAKE UP SLEEP 1 WAKE UP SIGNAL CONFIG LINK STARTED CLINKEN 0 OR SEREN 1 CLINKEN 1 UNLOCKED LOCKED CONFIG LINK CONFIG LINK SLEEP 0 SLEEP P...

Page 47: ...ialized and sent across serial link Video data received and deserialized LOW HIGH 1 0 0 SEREN SLEEP 1 POWER UP VALUE SEREN 0 FOR 8ms VIDEO LINK OPERATING VIDEO LINK PRBS TEST WAKE UP SLEEP 1 WAKE UP SIGNAL REVERSE LINK CONFIG LINK STARTED CLINKEN 0 OR SEREN 1 CLINKEN 1 UNLOCKED LOCKED CONFIG LINK CONFIG LINK SLEEP 0 SLEEP POWER ON IDLE POWER OFF ALL STATES PWDN LOW OR SLEEP 1 POWER DOWN OR POWER O...

Page 48: ...eserializer generate response values every 128 frames These values are compared internally internal comparison mode or can be compared in the host µC In addition the GMSL serializer deserializer provide response values for the enhanced link verification Enhanced link verification is an optional method of link verification for faster detection of loss of synchronization For this option the GMSL ser...

Page 49: ...GMSL DESERIALIZER 1 Initial state after power up Powers up waiting for HDCP authentication Powers up waiting for HDCP authentication 2 Makes sure that A V data not requiring protection low value content is available at the GMSL serializer inputs such as blue or informative screen Alternatively uses the FORCE_VIDEO and FORCE_AUDIO bits of the GMSL serializer to mask A V data at the input of the GMS...

Page 50: ...before restarting authentication 11 Waits for the VSYNC falling edge internal to the GMSL serializer and then sets the ENCRYPTION_ENABLE bit to 1 in the deserializer and GMSL serializer if the μC is not able to monitor VSYNC it can utilize the VSYNC_DET bit in the GMSL serializer Encryption enabled after the next VSYNC falling edge Decryption enabled after the next VSYNC falling edge 12 Checks tha...

Page 51: ...eck is successful go back to step 3 8 If RI does not match RI the link integrity check fails After the detection of failure of link integrity check the µC makes sure that A V data not requiring protection low value content is available at the GMSL serializer inputs such as blue or informative screen Alternatively the FORCE_VIDEO and FORCE_AUDIO bits of the GMSL serializer can be used to mask A V d...

Page 52: ...fails after 3 mismatches After the detection of failure of enhanced link integrity check the µC makes sure that A V data not requiring protection low value content is available at the GMSL serializer inputs such as blue or informative screen Alternatively the FORCE_VIDEO and FORCE_AUDIO bits of the GMSL serializer can be used to mask A V data input of the GMSL serializer 6 Writes 0 to the ENCRYPTI...

Page 53: ...ng for HDCP authentication All Power up waiting for HDCP authentication 2 Writes REPEATER 1 in RX_R1 Retries until proper acknowledge frame received Note This step must be completed before the first part of authentication is started between TX_B1 and RX_R1 by the µC_B step 7 For example to satisfy this requirement RX_R1 can be held at power down until µC_R is ready to write the REPEATER bit or µC_...

Page 54: ...ks start automatically if AUTOS of transmitters are low TX_R1 TX_R2 Starts serialization and transmits low value content A V data RX_D1 RX_D2 Locks to incoming data stream and outputs low value content A V data 5 Reads the locked bit of RX_R1 and makes sure the link between TX_B1 and RX_R1 is established Reads the locked bit of RX_D1 and makes sure the link between TX_R1 and RX_D1 is established R...

Page 55: ...s detected enables encryption on the TX_R1 RX_D1 and TX_R2 RX_D2 links TX_R1 TX_R2 Encryption enabled after next VSYNC falling edge RX_D1 RX_D2 Decryption enabled after next VSYNC falling edge 11 Waits for some time to allow µC_R to make the KSV list ready in RX_R1 Then polls reads the KSV_LIST_READY bit of RX_R1 regularly until proper acknowledge frame is received and bit is read as 1 Blocks cont...

Page 56: ...KSV list TX_B1 Triggered by µC_B s write of BINFO calculates hash value V on the KSV list BINFO and the secret value M0 15 Reads V from TX_B1 and V from RX_R1 If they match continues with authentication otherwise retries up to two more times 16 Searches for each KSV in the KSV list and BKSV of RX_R1 in the Key Revocation list 17 If keys are not revoked the second part of the authentication protoco...

Page 57: ...ser to prevent this contention by implementing a higher level protocol In addition the control channel does not provide arbitration between I2C masters on both sides of the link An acknowledge frame is not generated when communi cation fails due to contention If communication across the serial link is not required the µCs can disable the forward and reverse control channel using the FWDCCEN and RE...

Page 58: ...gh level a pulldown resistor to GND to set a low level or open to set a mid level For digital control use three state logic to drive the 3 level logic input Configuration Blocking The serializers can block changes to registers Set CFGBLOCK to make registers 0x00 to registers 0x1F as read only Once set the registers remain blocked until the supplies are removed or until PWDN is low Compatibility wi...

Page 59: ... short to the battery In coax mode leave the unused line fault inputs unconnected To detect the short together case refer to Application Note 4709 MAX9259 GMSL Line Fault Detection Table 20 lists the mapping for line fault types Internal Input Pulldowns The control and configuration inputs except 3 level inputs include a pulldown resistor to GND External pull down resistors are not needed Choosing...

Page 60: ...el or larger high frequency surface mount ceramic capacitors with sufficient voltage rating to withstand a short to battery to pass the lower speed reverse control channel signal Use capacitors with a case size less than 3 2mm x 1 6mm to have lower parasitic effects to the high speed signal Power Supply Circuits and Bypassing The serializers use an AVDD and DVDD of 1 7V to 1 9V and an LVDSVDD of 3...

Page 61: ... ESD tolerance is rated for Human Body Model IEC 61000 4 2 and ISO 10605 The ISO 10605 and IEC 61000 4 2 standards specify ESD tolerance for electronic systems The serial link inputs are rated for ISO 10605 ESD protection and IEC 61000 4 2 ESD protection All pins are tested for the Human Body Model The Human Body Model discharge components are CS 100pF and RD 1 5kΩ Figure 43 The IEC 61000 4 2 disc...

Page 62: ...um 111 4 spread spectrum D4 AUDIOEN 0 Disable I2S TDM channel 1 1 Enable I2S TDM channel D 3 2 PRNG 00 12 5MHz to 25MHz pixel clock 11 01 25MHz to 50MHz pixel clock 10 50MHz to 104MHz pixel clock 11 Automatically detect the pixel clock range D 1 0 SRNG 00 0 5 to 1Gbps serial bit rate 11 01 1 to 2Gbps serial bit rate 10 2 to 3 12Gbps serial bit rate 11 Automatically detect serial bit rate 0x03 D 7 ...

Page 63: ... 2 INTTYPE 00 Base mode uses I2C interface when I2CSEL 0 CDS 1 00 01 Base mode uses UART interface when I2CSEL 0 CDS 1 10 11 Local control channel disabled D1 REVCCEN 0 Disable reverse control channel from deserializer receiving 1 1 Enable reverse control channel from deserializer receiving D0 FWDCCEN 0 Disable forward control channel to deserializer sending 1 1 Enable forward control channel to d...

Page 64: ...08 D 7 4 0000 Reserved 0000 Read only D 3 2 LFNEG 00 Negative cable wire shorted to supply voltage 10 Read only 01 Negative cable wire shorted to ground 10 Normal operation 11 Negative cable wire disconnected D 1 0 LFPOS 00 Positive cable wire shorted to supply voltage 10 Read only 01 Positive cable wire shorted to ground 10 Normal operation 11 Positive cable wire disconnected 0x09 D 7 0 XXXXXXXX ...

Page 65: ...use 1000 Adjust X7PLL clock skew 50ps 1001 Adjust X7PLL clock skew 100ps 1010 Adjust X7PLL clock skew 200ps 1011 Adjust X7PLL clock skew 250ps 1100 Adjust X7PLL clock skew 300ps 1101 Adjust X7PLL clock skew 350ps 1110 Adjust X7PLL clock skew 400ps 1111 Do not Adjust X7PLL clock skew 0x0E D7 INVDE 0 Do not invert DE input 0 1 Invert DE input D 6 0 0000010 Reserved 0000010 0x0F D 7 1 I2CSRCA XXXXXXX...

Page 66: ...533kbps typ I2C to I2C master bit rate setting 111 837kbps typ I2C to I2C master bit rate setting D 1 0 I2CSLVTO 00 64µs typ I2C to I2C slave remote timeout 10 01 256µs typ I2C to I2C slave remote timeout 10 1024µs typ I2C to I2C slave remote timeout 11 No I2C to I2C slave remote timeout 0x14 D 7 4 CMLLVLCX 0000 Do not use 1010 0001 50mV CML coax output level 0010 100mV CML coax output level 0011 ...

Page 67: ...x16 D 7 0 XXXXXXXX Reserved XXXXXXXX 0x17 D7 HIGHIMM 0 Set reverse channel to legacy mode power up default value depends on GPO HIM pin value at power up 0 1 1 Set reverse channel to high immunity mode power up default value depends on GPO HIM pin value at power up D 6 0 0011111 Reserved 0011111 0x18 D 7 0 XXXXXXXX Reserved Read only 0x19 D 7 0 01001010 Reserved 01001010 0x1A D7 REVFAST 0 High Imm...

Page 68: ...D7 PD_HDCP 1 Power down HDCP circuits 0 HDCP circuits normal 0x00 D6 EN_INT_COMP 1 Internal comparison mode 0 µC comparison mode D5 FORCE_AUDIO 1 Force audio data to 0 0 Normal operation D4 FORCE_VIDEO 1 Force video data DFORCE value 0 Normal operation REGISTER ADDRESS BITS NAME VALUE FUNCTION DEFAULT VALUE 0x1B D7 INVSCK 0 Do not invert SCK input 0 1 Invert SCK input D6 INVWS 0 Do not invert WS i...

Page 69: ...n EN_INT_COMP 1 0 PJ does not match PJ or EN_INT_COMP 0 D1 R0_RI_MATCHED 1 RI matches RI when EN_INT_COMP 1 0 RI does not match RI or EN_INT_COMP 0 D0 BKSV_INVALID 1 BKSV is not valid 0 BKSV is valid 0x97 1 BCAPS Read write D 7 1 RESERVED 0x00 D0 REPEATER 1 Set to one if device is a repeater 0 Set to zero if device is not a repeater 0x98 to 0x9C 5 ASEED Read write internal random number generator ...

Page 70: ...write H4 part of SHA 1 hash value V read only of the transmitter when EN_INT_COMP 0 V read write of the receiver when EN_INT_COMP 1 0x00000000 0xB4 to 0xB5 2 BINFO Read write D 15 12 Reserved 0x0000 D11 MAX_CASCADE_EXCEEDED 1 Set to one if more than 7 cascaded devices attached 0 Set to zero if 7 or fewer cascaded devices attached D 10 8 DEPTH Depth of cascaded devices D7 MAX_DEVS_EXCEEDED 1 Set to...

Page 71: ...TX SCL LOCK IN INTOUT ADD2 CNTL3 ADD1 CNTL0 ADD0 IN CX TP WS SD DOUT28 CNTL2 SCK 4 99kΩ 4 99kΩ 45 3kΩ 45 3kΩ 49 9kΩ 49 9kΩ WS SD SCK MCLK PCLK RGBHV TO PERIPHERALS DISPLAY MAX9850 MAX9276 MAX9280 MAX9277 MAX9281 NOTE NOT ALL PULLUP PULLDOWN RESISTORS ARE SHOWN SEE PIN DESCRIPTION FOR DETAILS VIDEO DISPLAY APPLICATION LFLT INT MS LFLT MAX9277 MAX9281 3 12Gbps GMSL Serializers for Coax or STP Output...

Page 72: ...tegrated product No circuit patent licenses are implied Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time The parametric values min and max limits shown in the Electrical Characteristics table are guaranteed Other parametric values quoted in this data sheet are provided for guidance Maxim Integrated and the Maxim Integrated logo are trademark...

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