Maxim Integrated MAX9277, Manual

Page: 38 / 72

Acknowledge
The acknowledge bit is a clocked 9th bit that the recipient
uses to handshake receipt of each byte of data ( Figure
33 ). Thus, each byte transferred effectively requires nine
bits. The master generates the 9th clock pulse, and the
recipient pulls down SDA during the acknowledge clock
pulse. The SDA line is stable low during the high period
of the clock pulse. When the master is transmitting to the
slave device, the slave device generates the acknowl -
edge bit because the slave device is the recipient. When
the slave device is transmitting to the master, the master
generates the acknowledge bit because the master is the
recipient. The device generates an acknowledge even
when the forward control channel is not active. To prevent
acknowledge generation when the forward control chan -
nel is not active, set the I2CLOCACK bit low.
Slave Address
The serializers have 7-bit long slave addresses. The bit fol -
lowing a 7-bit slave address is the R/
W
bit, which is low for
a write command and high for a read command. The slave
address for the serializer is XX00XX01 for read commands
and XX00XX00 for write commands. See Figure 34 .
Bus Reset
The device resets the bus with the I
2
C START condition
for reads. When the R/
W
bit is set to 1, the serializers
transmit data to the master, thus the master is reading
from the device.
Format for Writing
Writes to the serializers comprise the transmission of the
slave address with the R/ W bit set to zero, followed by at
least one byte of information. The first byte of information
is the register address or command byte. The register
address determines which register of the device is to be
written by the next byte, if received. If a STOP (P) condi -
tion is detected after the register address is received, the
device takes no further action beyond storing the register
address ( Figure 35 ). Any bytes received after the register
address are data bytes. The first data byte goes into the
register selected by the register address, and subsequent
data bytes go into subsequent registers ( Figure 36 ). If
multiple data bytes are transmitted before a STOP con -
dition, these bytes are stored in subsequent registers
because the register addresses autoincrements.
Figure 33. Acknowledge
Figure 34. Slave Address
SCL
SDA
BY
TRANSMITTER
CLOCK PULSE FOR
ACKNOWLEDGE
START
CONDITION
SDA
BY
RECEIVER
1 2 8 9
S
SDA
X
ACK
SCL
MSB
LSB
X
X R/W
0 0 X 0
MAX9277/MAX9281 3.12Gbps GMSL Serializers for Coax or
STP Output Drive and LVDS Input
www.maximintegrated.com
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